StackOverflow Questions for Tag: immediate-operand

MustSee

Reputation: 151

How do I move a floating point constant into an FP register?

assemblyfloating-pointarm64neonimmediate-operand

Score: 3

Answers: 2

xiver77

Reputation: 2302

Why does SSE/AVX lack loading an immediate value?

assemblyx86sseinstruction-setimmediate-operand

Score: 7

Answers: 0

Capital S

Reputation: 53

Force arm64 gcc use instruction to construct double floating point number, no .rodata section

assemblygccfloating-pointarm64immediate-operand

Score: 3

Answers: 1

AVITAL

Reputation: 11

MIPS assembly `addi` instruction, how is a hexadecimal immediate interpreted?

assemblymipsimmediate-operand

Score: 0

Answers: 0

Ralf

Reputation: 1295

NASM Intel 64-bit mode: why does 32-bit constant 0xffffffff cause "warning: signed dword value exceeds bounds"

assemblyx86-64nasmimmediate-operand

Score: 4

Answers: 1

SnowDance1997

Reputation: 13

error: Impossible constraint in 'asm' "i"

cgccinline-assemblyarm64immediate-operand

Score: 0

Answers: 3

Lechius

Reputation: 325

What is SignImm in Branch Target Address formula context? (BTA)

assemblymipsmemory-addressimmediate-operandinstruction-encoding

Score: 1

Answers: 1

Jin

Reputation: 3

How to calculate the maximum range of BEQ instruction in risc-V?

assemblyrangeriscvimmediate-operand

Score: 0

Answers: 1

JSpruce

Reputation: 23

Instructions with Long (32 and 64 bit) immediate operands in RISC processors

assemblycpu-architectureinstruction-setimmediate-operandrisc

Score: 0

Answers: 3

rtburns

Reputation: 51

GNU assembler override size of immediate operand

assemblyx86disassemblygnu-assemblerimmediate-operand

Score: 5

Answers: 0

AlanPoser

Reputation: 147

ARMv5 and earlier MOV and MVN operands

assemblyarmmovarm7immediate-operand

Score: 2

Answers: 2

Hysii

Reputation: 772

XOR operand type mismatch

assemblyx86-64shellcodeimmediate-operand

Score: 0

Answers: 0

4Matt

Reputation: 251

Understanding address assignment to registers via assembly instructions

assemblycpu-architecturemachine-codeinstruction-setimmediate-operand

Score: 0

Answers: 3

Betty

Reputation: 161

How to load an immediate number to a register in RV32I Base Instruction Set?

assemblyriscvimmediate-operand

Score: 7

Answers: 1

Daniel Ilie

Reputation: 127

Understand EQU and >> operators on them in RISC-V assembly, with LUI and ADDI

assemblyriscvimmediate-operand

Score: 3

Answers: 1

Razi Awad

Reputation: 53

How does LUI/ORI on MIPS work to create a 32-bit constant value?

assemblymipsinstruction-setimmediate-operand

Score: 5

Answers: 2

Li Hanyuan

Reputation: 556

RISC-V build 32-bit constants with LUI and ADDI

assemblyconstantsriscvimmediate-operand

Score: 22

Answers: 4

Reputation: 37

RISC-V U-Format instruction immediate confusion

assemblyriscvmachine-codeimmediate-operandinstruction-encoding

Score: 0

Answers: 1

Nikolai Savulkin

Reputation: 759

What are the common ways instruction decoders deal with using constants over registers in microcontrollers?

assemblycpucpu-architectureimmediate-operand

Score: 0

Answers: 1

Mzq

Reputation: 1854

ARMv7 T3 encoding for adds

assemblyarmthumbimmediate-operandinstruction-encoding

Score: 0

Answers: 1

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StackOverflow Questions for Tag: immediate-operand

How do I move a floating point constant into an FP register?

Why does SSE/AVX lack loading an immediate value?

Force arm64 gcc use instruction to construct double floating point number, no .rodata section

MIPS assembly `addi` instruction, how is a hexadecimal immediate interpreted?

NASM Intel 64-bit mode: why does 32-bit constant 0xffffffff cause &quot;warning: signed dword value exceeds bounds&quot;

error: Impossible constraint in &#39;asm&#39; &quot;i&quot;

What is SignImm in Branch Target Address formula context? (BTA)

How to calculate the maximum range of BEQ instruction in risc-V?

Instructions with Long (32 and 64 bit) immediate operands in RISC processors

GNU assembler override size of immediate operand

ARMv5 and earlier MOV and MVN operands

XOR operand type mismatch

Understanding address assignment to registers via assembly instructions

How to load an immediate number to a register in RV32I Base Instruction Set?

Understand EQU and &gt;&gt; operators on them in RISC-V assembly, with LUI and ADDI

How does LUI/ORI on MIPS work to create a 32-bit constant value?

RISC-V build 32-bit constants with LUI and ADDI

RISC-V U-Format instruction immediate confusion

What are the common ways instruction decoders deal with using constants over registers in microcontrollers?

ARMv7 T3 encoding for adds

NASM Intel 64-bit mode: why does 32-bit constant 0xffffffff cause "warning: signed dword value exceeds bounds"

error: Impossible constraint in 'asm' "i"

Understand EQU and >> operators on them in RISC-V assembly, with LUI and ADDI