StackOverflow Questions for Tag: memory-fences

knivil

Reputation: 805

Which memory barriers do I need, to make the writes to image in thread A visible in Thread B?

arrayscmultithreadingmemory-barriers

Score: 0

Answers: 1

Aimin Huang

Reputation: 175

Understanding memory order relaxed in C++

c++concurrencyatomicmemory-barriers

Score: 7

Answers: 2

Alex V.

Reputation: 19

Write to same color attachment from multiple batches

vulkanmemory-barriers

Score: 0

Answers: 1

pveentjer

Reputation: 11307

How do modern Intel x86 CPUs implement the total order over stores

x86intelcpu-architecturememory-barriersmesi

Score: 8

Answers: 2

k1r1t0

Reputation: 769

What is Memory Ordering Nuke in Intel CPUs?

x86cpu-architectureintelmemory-barriersspeculative-execution

Score: 1

Answers: 0

song xs

Reputation: 71

Does gcc treat relaxed atomic operation as a Compiler-fence?

c++gccatomicmemory-barriersmemory-model

Score: 5

Answers: 1

Gilgamesz

Reputation: 5063

Atomicity of loads and stores on x86

c++x86cpu-architectureatomicmemory-barriers

Score: 38

Answers: 2

untitled

Reputation: 429

Will memory write be visible after sending an IPI on x86?

assemblyx86operating-systemmemory-barriersmsr

Score: 8

Answers: 3

ron burgundy

Reputation: 73

Are acquire-release semantics transitive across threads?

c++multithreadingconcurrencymemory-barriersstdatomic

Score: 1

Answers: 1

relatively_random

Reputation: 5126

How does the common 4 thread example for demonstrating sequential consistency work on a system with cache coherence?

c++atomicmemory-barrierslock-freestdatomic

Score: 0

Answers: 0

Dmytro Kostenko

Reputation: 235

Why Did LOCK-prefixed Instructions Become Preferred Over MFENCE for Memory Fences in the JVM on x86?

assemblyx86cpu-architecturememory-barriersinstruction-set

Score: 1

Answers: 0

Ervin Xie

Reputation: 11

Dequeued item exists but std::counting_semaphore::try_acquire() fails in single-consumer MPSC queue

c++memoryconcurrencymemory-barriers

Score: 1

Answers: 1

pveentjer

Reputation: 11307

ARMv8.3 meaning of rcpc

armcpu-architecturememory-barriersmemory-modelarmv8

Score: 7

Answers: 2

Dmytro Kostenko

Reputation: 235

How Does the Store Buffer Drain in x86 Architecture Work?

x86cpu-architectureintelmemory-barriersmemory-model

Score: 1

Answers: 0

Lantanar

Reputation: 35

How do I thread safely write a struct to memory?

linuxmultithreadingrustx86-64memory-barriers

Score: 0

Answers: 0

Hermann Speiche

Reputation: 924

Do C90-compliant compilers have to take into account instruction reordering by the CPU?

cassemblystandardsvolatilememory-barriers

Score: 5

Answers: 2

Ryaaan

Reputation: 25

C++ memory order on Apple M1 chip not work: reordering happens even with seq_cst in a StoreStore / LoadLoad litmus test?

c++atomicapple-m1arm64memory-barriers

Score: 1

Answers: 2

Johan

Reputation: 76537

What is an error barrier, and what does it do?

assemblycudaatomicnvidiamemory-barriers

Score: 4

Answers: 0

hao

Reputation: 1

Why different threads can see different memory operation orders?

c++c++11memory-barriersmemory-model

Score: -1

Answers: 1

mentalmushroom

Reputation: 2467

Understanding std::kill_dependency

c++concurrencyatomicmemory-barrierscarries-dependency

Score: 6

Answers: 1

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