StackOverflow Questions for Tag: memory-model

mpoeter

Reputation: 2969

Visibility of atomic operations with seq-cst fences in C++20

c++language-lawyermemory-barriersstdatomicmemory-model

Score: 1

Answers: 1

Dhwani Katagade

Reputation: 1290

Does this transitive happens-before use case need sequential consistency or will acquire/release suffice?

c++c++11stdatomicmemory-modelhappens-before

Score: 4

Answers: 2

ledonter

Reputation: 1719

How is modification order of a variable defined in C++?

c++c++20stdatomicmemory-model

Score: 6

Answers: 2

Lifu Huang

Reputation: 12869

CUDA memory model: why acquire fence is not needed to prevent load-load reordering?

c++cudamemory-model

Score: 4

Answers: 1

TSK

Reputation: 751

Why release sequence can only contain read-modify-write but not pure write

c++cpu-architectureatomicstdatomicmemory-model

Score: 6

Answers: 1

user2138149

Reputation: 17266

How does Julia know what the type of some object is? What is the memory layout of a reference to a `Vector{Int64}`?

juliatype-inferencetype-systemsmemory-model

Score: 1

Answers: 1

song xs

Reputation: 81

Does gcc treat relaxed atomic operation as a Compiler-fence?

c++gccatomicmemory-barriersmemory-model

Score: 5

Answers: 1

NGC6543

Reputation: 179

Are all C# writes 'volatile'?

c#memoryvolatilememory-model

Score: 1

Answers: 1

Dmytro Kostenko

Reputation: 235

Can compiler optimizations avoid writing to memory by operating exclusively in registers?

javamultithreadingoptimizationx86memory-model

Score: 1

Answers: 2

pveentjer

Reputation: 11392

ARMv8.3 meaning of rcpc

armcpu-architecturememory-barriersmemory-modelarmv8

Score: 7

Answers: 2

Dmytro Kostenko

Reputation: 235

How Does the Store Buffer Drain in x86 Architecture Work?

x86cpu-architectureintelmemory-barriersmemory-model

Score: 1

Answers: 0

user3188445

Reputation: 4784

How does C++23 happens before apply to std::memory_order_seq_cst?

c++language-lawyermemory-modelrelaxed-atomics

Score: 2

Answers: 2

breaker00

Reputation: 187

What does memory_order_consume really do?

c++cpu-architecturelock-freememory-modelstdatomic

Score: 14

Answers: 4

Julian Stecklina

Reputation: 1281

Can atomic loads be merged in the C++ memory model?

c++language-lawyercompiler-optimizationmemory-modelstdatomic

Score: 22

Answers: 2

hao

Reputation: 1

Why different threads can see different memory operation orders?

c++c++11memory-barriersmemory-model

Score: -1

Answers: 1

heturing

Reputation: 150

How sequentially consistent ordering in c++ define a total order?

c++multithreadingmemory-model

Score: 2

Answers: 3

kan

Reputation: 28981

std::atomic<int> memory_order_relaxed VS volatile sig_atomic_t in a multithreaded program

c++multithreadingvolatilememory-modelstdatomic

Score: 9

Answers: 1

idle_cycles

Reputation: 173

Understanding Memory Controller RPQ/WPQ ordering guarantees for loads and ntstores

assemblyx86x86-64cpu-architecturememory-model

Score: 2

Answers: 1

Amit

Reputation: 1160

Does re-writing the same value to a memory location count as modifying the memory? (in the context of multi-threading)

c++multithreadingc++11memory-modeldata-race

Score: 7

Answers: 2

pranith

Reputation: 879

How can a writer after a barrier be visible before a write preceding the barrier?

linux-kernelshared-memorymemory-model

Score: 0

Answers: 2

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StackOverflow Questions for Tag: memory-model

Visibility of atomic operations with seq-cst fences in C++20

Does this transitive happens-before use case need sequential consistency or will acquire/release suffice?

How is modification order of a variable defined in C++?

CUDA memory model: why acquire fence is not needed to prevent load-load reordering?

Why release sequence can only contain read-modify-write but not pure write

How does Julia know what the type of some object is? What is the memory layout of a reference to a `Vector{Int64}`?

Does gcc treat relaxed atomic operation as a Compiler-fence?

Are all C# writes &#39;volatile&#39;?

Can compiler optimizations avoid writing to memory by operating exclusively in registers?

ARMv8.3 meaning of rcpc

How Does the Store Buffer Drain in x86 Architecture Work?

How does C++23 happens before apply to std::memory_order_seq_cst?

What does memory_order_consume really do?

Can atomic loads be merged in the C++ memory model?

Why different threads can see different memory operation orders?

How sequentially consistent ordering in c++ define a total order?

std::atomic&lt;int&gt; memory_order_relaxed VS volatile sig_atomic_t in a multithreaded program

Understanding Memory Controller RPQ/WPQ ordering guarantees for loads and ntstores

Does re-writing the same value to a memory location count as modifying the memory? (in the context of multi-threading)

How can a writer after a barrier be visible before a write preceding the barrier?

Are all C# writes 'volatile'?

std::atomic<int> memory_order_relaxed VS volatile sig_atomic_t in a multithreaded program