StackOverflow Questions for Tag: opcodes

Alfred

Reputation: 61783

What does a \ (backslash) in front of function names mean?

phpnamespacesopcodeopcache

Score: 249

Answers: 5

bobuhito

Reputation: 297

Mysterious ARM Opcode

armdisassemblycortex-mopcodethumb

Score: 1

Answers: 1

Daidamai

Reputation: 51

Why are 'opcode' field and 'funct' field apart in MIPS?

mipscpu-architectureinstruction-setopcodeinstruction-encoding

Score: 4

Answers: 2

Don J

Reputation: 3

RISCV resolving opcode

riscvmachine-codeopcodeinstruction-encoding

Score: 0

Answers: 1

Stas Buzuluk

Reputation: 865

Disassembling bytecode into opcodes across different EVM versions

ethereumsoliditydecompilingopcodeevm

Score: 0

Answers: 2

Błażej Michalik

Reputation: 5055

Assembly: why some x86 opcodes are invalid in x64?

assemblyx86x86-64cpu-architectureopcode

Score: 8

Answers: 2

Jim Sawyer

Reputation: 143

Any useful way (amd64) to effect a transfer like this? pc <-- (sp) [Note the absense of auto-decrement]

optimizationx86-64opcode

Score: 0

Answers: 0

corkeygo

Reputation: 1

Explaining LLVM for loop

for-loopllvmopcode

Score: 0

Answers: 1

Perfect Paradox

Reputation: 1

ANSI C90 68hc11 Assembly Language, Opcode Error Trapping

assemblyc89opcode68hc11

Score: 0

Answers: 0

Anton Shkindzer

Reputation: 63

Adding new custom opcode to solidity

ethereumsolidityopcode

Score: 1

Answers: 1

Dipsie Camila

Reputation: 11

How can I write a short bitwise code as jmp $ without directives?

assemblynasmintelopcode

Score: 0

Answers: 0

Uchia Itachi

Reputation: 5315

How to determine if a word(4 bytes) is a 16-bit instruction or 32-bit instruction?

armdecodingcortex-marmv7opcode

Score: 3

Answers: 1

Rowhawn

Reputation: 1479

What exactly does the 3-operand imul instruction do in ia-32 assembly?

assemblyx86instruction-setinstructionsopcode

Score: 6

Answers: 2

bob123123123123

Reputation: 57

System.InvalidProgramException Common Language Runtime detected an invalid program for Reflection

c#reflectionreflection.emitopcodeflee

Score: 0

Answers: 0

Mark Thomas

Reputation: 55

How does the VM OS issue privileged Opcodes without being terminated by the Host OS/CPU?

operating-systemvirtual-machinecpu-architectureopcode

Score: 0

Answers: 2

Alan Campbell

Reputation: 417

List of Cortex-M4 Opcodes

armopcodeinstruction-setcortex-m

Score: 6

Answers: 2

Evan

Reputation: 442

how to detect the instruction boundary while designing a disassembler?

assemblyx86-64disassemblymachine-codeopcode

Score: 1

Answers: 0

Evan

Reputation: 442

machine code FF 25 should have 64-bit operand but actually only 32-bit is available

assemblyx86-64machine-codeopcode

Score: 3

Answers: 1

NannerBannaner23

Reputation: 1

Create a Field using FieldBuilder and add one to Field Value in MethodBuilder ILCode Emit

c#opcodedynamicmethodilgenerator

Score: 0

Answers: 1

WickedXXX

Reputation: 27

OPCUA subscribing to all events

opcopcodesiemenshoneywellunified-automation-sdk

Score: 1

Answers: 0

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StackOverflow Questions for Tag: opcodes

What does a \ (backslash) in front of function names mean?

Mysterious ARM Opcode

Why are &#39;opcode&#39; field and &#39;funct&#39; field apart in MIPS?

RISCV resolving opcode

Disassembling bytecode into opcodes across different EVM versions

Assembly: why some x86 opcodes are invalid in x64?

Any useful way (amd64) to effect a transfer like this? pc &lt;-- (sp) [Note the absense of auto-decrement]

Explaining LLVM for loop

ANSI C90 68hc11 Assembly Language, Opcode Error Trapping

Adding new custom opcode to solidity

How can I write a short bitwise code as jmp $ without directives?

How to determine if a word(4 bytes) is a 16-bit instruction or 32-bit instruction?

What exactly does the 3-operand imul instruction do in ia-32 assembly?

System.InvalidProgramException Common Language Runtime detected an invalid program for Reflection

How does the VM OS issue privileged Opcodes without being terminated by the Host OS/CPU?

List of Cortex-M4 Opcodes

how to detect the instruction boundary while designing a disassembler?

machine code FF 25 should have 64-bit operand but actually only 32-bit is available

Create a Field using FieldBuilder and add one to Field Value in MethodBuilder ILCode Emit

OPCUA subscribing to all events

Why are 'opcode' field and 'funct' field apart in MIPS?

Any useful way (amd64) to effect a transfer like this? pc <-- (sp) [Note the absense of auto-decrement]