StackOverflow Questions for Tag: questasim

AWESOMENESS FOREVER
AWESOMENESS FOREVER

Reputation: 11

Questasim tool showing error after updating code and re running for schematic

Score: -1

Views: 377

Answers: 1

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HD12345
HD12345

Reputation: 11

Questa Error "UI-Msg: (vish-4014) No objects found matching " while running from quartus

Score: 0

Views: 628

Answers: 1

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harinath Digital
harinath Digital

Reputation: 1

How do I invoke Clock-Domain Crossing in Questa CDC?

Score: -2

Views: 1076

Answers: 1

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benjstark
benjstark

Reputation: 95

What should I do to make the interface visible to some components?

Score: 0

Views: 258

Answers: 1

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benjstark
benjstark

Reputation: 95

Why can the argument of `uvm_info not be convert2string()?

Score: 1

Views: 265

Answers: 1

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benjstark
benjstark

Reputation: 95

What is the meaning of numbers in UVM_INFO?

Score: 2

Views: 280

Answers: 1

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Don Rumata
Don Rumata

Reputation: 11

Module's parameter initialization troubles

Score: 1

Views: 98

Answers: 1

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Don Rumata
Don Rumata

Reputation: 11

Module's parameter initialization troubles (updated)

Score: 0

Views: 54

Answers: 1

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a_bet
a_bet

Reputation: 390

SystemVerilog QuestaSim - Pass string to $fdumpvars to save multiple VCD files

Score: 1

Views: 705

Answers: 2

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efe373
efe373

Reputation: 171

EDA Playground EPWave $dumpfile error: no vcd file found

Score: 1

Views: 7517

Answers: 1

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Jo-Jo Smith
Jo-Jo Smith

Reputation: 21

Set Questa Sim Double-Click Editor

Score: 0

Views: 860

Answers: 2

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Tsr
Tsr

Reputation: 11

verification using Questasim

Score: 0

Views: 418

Answers: 1

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jarno
jarno

Reputation: 149

Formatting $info

Score: 0

Views: 933

Answers: 2

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grandslam47
grandslam47

Reputation: 9

No data message in ModelSim

Score: 0

Views: 846

Answers: 1

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ex1led
ex1led

Reputation: 469

Dynamic generation of signal spies in testbench

Score: 0

Views: 390

Answers: 1

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Vineeth
Vineeth

Reputation: 111

Installing UVM 1.2 in Questasim 10.2 windows

Score: 1

Views: 2582

Answers: 2

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Nmarks
Nmarks

Reputation: 11

Is it possible to testbench VHDL designs with verilog

Score: 0

Views: 394

Answers: 0

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Jim Lewis
Jim Lewis

Reputation: 3983

Redirecting output of tcl proc to file and output (like tee) Part 2

Score: 0

Views: 539

Answers: 1

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None
None

Reputation: 2433

How to override localparam? -GPARAM=VAL not working

Score: 0

Views: 1984

Answers: 1

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Joe
Joe

Reputation: 21

In Modelsim/Questasim is there a way to increase the thickness of the wave lines?

Score: 1

Views: 1771

Answers: 2

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