StackOverflow Questions for Tag: risc

Sotaro Suzuki

Reputation: 21

I cannot find a solution to muliply unsigned integers

assemblyriscvriscrars-simulator

Score: 0

Answers: 0

Neeraj Singh

Reputation: 169

Different structures in out of order processors

x86-64cpu-architecturerisc

Score: 0

Answers: 0

roffensive

Reputation: 574

Why the RISC instruction sets usually do not contain register to register copy instruction?

assemblycpu-architectureinstruction-setrisc

Score: 2

Answers: 1

exiturnor

Reputation: 57

What is the value x12 at the end of the execution of this instruction in RISC-V? (WITHOUT RARS)

c++architectureriscvinstruction-setrisc

Score: 0

Answers: 1

beginner_dv

Reputation: 38

CISC mul vs RISC mul instruction

risc

Score: 0

Answers: 1

Dillon Burton

Reputation: 363

Assembly language st and ld

assemblymemorysparcrisc

Score: 1

Answers: 1

Constantinos Petrakis

Reputation: 91

pow(float x, float y) in RISC Assembly

mipsnumericpowapproximationrisc

Score: 0

Answers: 0

J Seabolt

Reputation: 2978

How are POSIX and RISC/CISC related

posixrisc

Score: 0

Answers: 1

user366312

Reputation: 16894

Are WAW and WAR hazards unique to RISC processors?

microprocessorsrisc

Score: 1

Answers: 1

Abdullah Meda

Reputation: 119

Assembly language files. Whats the differnce?

assemblyarmrisc

Score: -1

Answers: 2

ThePom

Reputation: 95

Risc processor the Negation of a register

assemblycpu-architectureinstruction-setrisc

Score: -2

Answers: 1

user1998844

Reputation: 467

Are PUSH/POP instructions considered RISC or CISC?

assemblycpu-architectureinstruction-setrisc

Score: 12

Answers: 2

user11224591

Reputation:

Do RISC processors not have backward compatibility?

armcpu-architecturebackwards-compatibilityinstruction-setrisc

Score: -1

Answers: 2

Pzet

Reputation: 490

Why are CISC instructions considered to be easier/faster to compile than RISC instructions?

compiler-constructioncode-generationcpu-architectureprocessorrisc

Score: 0

Answers: 0

YaserM

Reputation: 187

CISC and RISC architectures

computer-sciencecpu-architecturerisc

Score: 2

Answers: 2

Olivia Pearls

Reputation: 139

When does the pipeline take 2 decode stages when there is a RAW dependency in 2 successive instructions

cpu-architecturepipeliningrisc

Score: 0

Answers: 1

Adam Smith

Reputation: 511

Why are there two ways to multiply arbitrary signed numbers in MIPS?

assemblymipsinstruction-setrisc

Score: 7

Answers: 1

LordOfFlies

Reputation: 11

Does the store word (sw) instruction in MIPS have dependencies on both the rt and rs field?

mipsrisc

Score: 1

Answers: 0

Prawn Hongs

Reputation: 451

Which program will be bigger in size - RISC or CISC?

risc

Score: -1

Answers: 1

Sabir Asmare

Reputation: 75

Renesas M32R Processor preocedural call and returns

assemblyrisc

Score: 1

Answers: 1

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