StackOverflow Questions for Tag: thumb

float93

Reputation: 11

Calling function in payload at ARMv7

assemblyarmcortex-mshellcodethumb

Score: 1

Answers: 1

Guy S.

Reputation: 45

How to prevent IDA 8.4 from switching arm disassembly from thumb to arm modes on every instruction step

remote-debuggingidathumbsegger-jlink

Score: 0

Answers: 0

ugger B

Reputation: 11

Is the bootloader correctly jumping to the application?

armembeddedstartupbootloaderthumb

Score: 1

Answers: 0

Alexander

Reputation: 20224

Compile thumb1 only

gccarmthumb

Score: 6

Answers: 1

w_m0zart

Reputation: 1

arm cbz instruction with apparent always non-zero register value

armreverse-engineeringfirmwarethumbghidra

Score: 0

Answers: 0

johnsondavies

Reputation: 447

Is there an ARM Thumb-1 instruction that will zero a register without affecting the flags?

armthumb

Score: 1

Answers: 0

Echelon X-Ray

Reputation: 323

Ways to perform bitwise operations with symbols inside Assembly constants?

assemblyarmgnu-assemblerfirmwarethumb

Score: 2

Answers: 0

Mika Vatanen

Reputation: 4017

How to set the instruction size (16 bit or 32 bit) for a function on ARM thumb?

rustarmthumb

Score: 0

Answers: 1

Lalit Arora

Reputation: 1

How TBB and DCB work in branching the flow?

assemblyarmcortex-mthumb

Score: 0

Answers: 0

bobuhito

Reputation: 297

Mysterious ARM Opcode

armdisassemblycortex-mopcodethumb

Score: 1

Answers: 1

mrbean

Reputation: 581

How is this ARM (Thumb) LDR Instruction being calculated?

armcortex-mthumb

Score: -1

Answers: 1

kyb

Reputation: 8141

Is it redundant to check if a modulo operation is needed, then performing it?

c++cperformancearmthumb

Score: 46

Answers: 4

yo3hcv

Reputation: 1669

Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example

assemblyarmcortex-mthumbinstruction-encoding

Score: 0

Answers: 0

OpOp_1

Reputation: 91

Why the Link register in FIQ mode will be instruction address plus 4 in thumb mode instead of instruction address plus 2?

arminterruptarmv7thumbcortex-r

Score: 1

Answers: 1

Fabian

Reputation: 434

Is CMPS a valid ARM/THUMB instruction?

assemblyarminstruction-setinstructionsthumb

Score: 0

Answers: 2

RRIDDICC

Reputation: 129

gcc inline asm / constraints / "r" relates to "l" like "g" to ...?

assemblygccarminline-assemblythumb

Score: 0

Answers: 1

KMC

Reputation: 20046

Ordering of registers in PUSH and POP brackets

armstackcortex-mthumb

Score: 3

Answers: 2

Chimess

Reputation: 25

Loading a the address of a pointer into a register inline thumb assembly

cpointersinline-assemblycpu-registersthumb

Score: 2

Answers: 1

Maxpm

Reputation: 25571

Why do forward reference ADR instructions assemble with even offsets in Thumb code?

assemblyarmgnu-assemblerthumb

Score: 4

Answers: 3

71GA

Reputation: 1391

What is the difference between the ARM, Thumb and Thumb 2 instruction encodings?

armthumb

Score: 80

Answers: 6

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StackOverflow Questions for Tag: thumb

Calling function in payload at ARMv7

How to prevent IDA 8.4 from switching arm disassembly from thumb to arm modes on every instruction step

Is the bootloader correctly jumping to the application?

Compile thumb1 only

arm cbz instruction with apparent always non-zero register value

Is there an ARM Thumb-1 instruction that will zero a register without affecting the flags?

Ways to perform bitwise operations with symbols inside Assembly constants?

How to set the instruction size (16 bit or 32 bit) for a function on ARM thumb?

How TBB and DCB work in branching the flow?

Mysterious ARM Opcode

How is this ARM (Thumb) LDR Instruction being calculated?

Is it redundant to check if a modulo operation is needed, then performing it?

Which instruction encoding is supported by a ARM processor, particularly a Cortex M0, STM32F0 one for example

Why the Link register in FIQ mode will be instruction address plus 4 in thumb mode instead of instruction address plus 2?

Is CMPS a valid ARM/THUMB instruction?

gcc inline asm / constraints / &quot;r&quot; relates to &quot;l&quot; like &quot;g&quot; to ...?

Ordering of registers in PUSH and POP brackets

Loading a the address of a pointer into a register inline thumb assembly

Why do forward reference ADR instructions assemble with even offsets in Thumb code?

What is the difference between the ARM, Thumb and Thumb 2 instruction encodings?

gcc inline asm / constraints / "r" relates to "l" like "g" to ...?