What the role of a target in a Makefile?

Question

I was under an impression that the left hand side of the colon : represent target i.e. the executable file, and the right hand side represents 'dependencies', i.e. the files needed to produce the said target.

hello : hello.c
    gcc hello.c -Wall -o hello

So, I thought the target 'hello' is the name of the final executable file.

executableHelloWorldFile : hello.c
    gcc hello.c -Wall -o hello

but, when I changed 'hello' to 'executableHelloWorldFile', nothing changed in the output.

I know how to create the target, but here I wish to understand that in what matters does a target help a Makefile?

Answer 1

You need to use the appropriate variables in the rule: $@ is the target $^ are the dependencies. In your case this should be:

executableHelloWorldFile : hello.c
    gcc $^ -Wall -o $@

Or when you only need to refer to the first dependency, use $<:

executableHelloWorldFile : hello.c
    gcc $< -Wall -o $@

Answer 2

Firstly, Target is assumed to be a file, which, if doesn't exist or its timestamp is later than any of its dependencies, is remade. If you change the target name from the actual filename to something random, your target will always be remade, because that arbitrary file you are fooling make with doesn't exist and it is not created when make runs the commands you specified.

Edit: your compiler has no idea make invokes it, it executes exactly the instructions you gave it (as every computer program does and should do). If you say '-o hello', it will write the binary to the file 'hello' regardless to the bogus target name you came up with.

Answer 3

A make target is basically a file that you want rebuilt.

Make can't divine what you want built, so you have to tell it, implicitly or explicitly, what it should build. Often, the first target in the file is a name such as 'all' and if you run 'make' without any explicit target, it will build the first target listed in the makefile. However, some makefiles do not specify any target; then you must specify one on the command line. Or, if you don't want the default target built, then you must specify the target that you do want built.

A makefile will usually include code to make your program, install your program, clean up afterward, and other things.

so the word target could be various keywords, such as all, install, clean, etc.

It's a way of saying make something. make all implies do everything

Answer 4

make executes the command you gave it. If that command doesn't create the target, it's your fault for writing the wrong command. The significant difference is that if you have the target specified correctly, you can run make twice in a row and it will know the second time that the target is up to date and doesn't need to be rebuilt. When the target isn't actually created by the command, if you run make twice in a row, the second one will needlessly rerun the command.

Some targets (like all and clean) are conventionally included in Makefiles without actually being existing files. They represent bigger actions that the user can request with commands like make clean in which the commands must be run every time.

Answer 5

1. Yes, in your example, the target "hello" happens to result in building the .exe "hello".

2. But no, you can trigger any action (or combination of actions) with a target.

   For example, "make clean", "make build" and "make install" and "make all" are common commands. They trigger the makefile to 1) clean up any "junk" that's already been built, 2) recompile the project, 3) install the project or 4) do everything

3. To answer your question, a "target" is just a way to tell a makefile to "do something".

   In your example, the target will invoke "gcc". But it will invoke it if - and only if - the source file "hello.c" is out of date.

4. A makefile usually consists of many targets, rules and defines.

   A component usually consists of multiple sub-projects, each with its own makefile.

'Hope that helps .. PSM