CODEWITHSUNDEEP
makefilegnu-makemultiple-makefiles
user1511590
user1511590

Reputation: 71

How to Overwrite a variable in makefile from terminal

I have created a simple makefile i.e.

COMMON=hello
all:
  gcc $(COMMON).c -o $(COMMON).o

The directory in which I am running the makefile contains three files: hello.c add.c multiply.c factorial.c and subtraction.c.

When I am compiling this in the terminal using the make command, the hello gets printed. Now I want to make changes in the program such that when I write "make add" or "make multiply" or "make factorial", the corresponding program will compile.

Upvotes: 2

Views: 3169

Answers (1)

tripleee
tripleee

Reputation: 189387

Just supply it on the command line.

make COMMON=bye

If the target is predictable from file names in the current directory, you don't really need a Makefile at all, because Make already knows how to make multiply from multiply.c.

.PHONY: all
all: hello add multiply factorial

If you really want an explicit recipe, try something like this.

%: %.c
        gcc -o $@ $^

Upvotes: 4

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