CODEWITHSUNDEEP
makefilegnu-make
Botnic
Botnic

Reputation: 163

Makefile: Modify variable in target

I have a variable containing a list of files. They will be passed to my simulation environment.

VHDL_SOURCES += $(PWD)/common/ip/file1.vhd \
                $(PWD)/common/ip/file2.vhd \
                $(PWD)/common/ip/file3.vhd \
                $(PWD)/common/ip/file4.vhd \

One of the targets creates a bunch of new files and they should be added to the list.

# sim target: Add requirement filelist.txt 
.PHONY: sim
sim: add_xilip_sources


# all other definitions are defined in the common makefile
include $(PWD)/scripts/cocotb/common_makefile/Makefile

.PHONY: add_xilip_sources
add_xilip_sources: $(BUILD_PWD)/filelist.txt
    XILIP_FILES = $(shell cat $<) # read the filelist into an variable
    # prepend the new filelist to the VHDL_SOURCES list. 

$(BUILD_PWD)/filelist.txt: $(SCRIPT_PWD)/make_switch_ip.tcl
    vivado -mode tcl -source $(SCRIPT_PWD)/make_switch_ip.tcl

How can I modify the variable in my target?

Upvotes: 0

Views: 232

Answers (1)

Andreas
Andreas

Reputation: 5301

You can't. Make is declarative, or two-step; first specifying the build environment, then executing. You can't modify the build environment such as variables while executing it, or at least not between different recipes.

What you can do is use files instead of variables:

# vhdl_sources.txt containing VHDL_SOURCES
# vhdl_sources.txt.full containing VHDL_SOURCES plus generated filelist.txt content
vhdl_sources.txt.full: $(BUILD_PWD)/filelist.txt vhdl_sources.txt
    cat $^ > $@

Upvotes: 1

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