CODEWITHSUNDEEP
makefiletarget
paulgray
paulgray

Reputation: 683

Change Makefile variable value inside the target body

Is there a way to reassign Makefile variable value inside of the target body?

What I am trying to do is to add some extra flags for debug compilation:

%.erl: %.beam
    $(ERLC) $(ERLFLAGS) -o ebin $<

test: clean debug_compile_flag compile compile_test

debug_compile:
    $(ERLCFLAGS) += -DTEST

So if I invoke test target I would like to clean up my environment, add some new flags (like -DTEST to the existing ones), compile the whole code once again (first sources, then test modules).

I do not want to copy/paste the code for compiling with some new flags set since there is a lot of logic put here and there.

Is there some easy way to redefine the variable value so I can reuse the existing code?

Upvotes: 68

Views: 97145

Answers (6)

Csongor Halmai
Csongor Halmai

Reputation: 3915

Here is the solution I use:

PASSWORD = abc123

main: sub
    @echo "in main" $(PASSWORD)

sub:
    @echo "in sub" $(PASSWORD)
    $(eval PASSWORD=qwerty)
    @echo "in sub" $(PASSWORD)

If you run make main then the output is:

in sub abc123
in sub qwerty
in main qwerty

You can see that the original value "abc123" is overwritten in the sub and the new value "qwerty" is visible at the main level.

Upvotes: 8

placid chat
placid chat

Reputation: 189

To override on the command line try something like:

make prefix=<path to new dir> install

This won't change Makefile, but will alter the variable.

Upvotes: 0

Alberto Chiusole
Alberto Chiusole

Reputation: 2794

I wanted to add a target in a makefile to run tests, which implied recompiling the source code with some debug flags. Ian's answer: https://stackoverflow.com/a/15561911/ was the only solution that worked.

Here's the Makefile I came up with, which guaranties the order of execution when running make tests:

TARGET     = a.out

CC         = g++
GENERIC_F  = -Wall -Wextra -I. -Idoctest/doctest/

CFLAGS     = -O0 -std=c++11 $(GENERIC_F)
DEBUG_MODE = -DDEBUG

LINKER     = g++
LFLAGS     = $(GENERIC_F) -lm

SRCDIR     = src
OBJDIR     = build
BINDIR     = bin

SOURCES    = $(wildcard $(SRCDIR)/*.cc)
INCLUDES   = $(wildcard $(SRCDIR)/*.h)
OBJECTS    = $(SOURCES:$(SRCDIR)/%.cc=$(OBJDIR)/%.o)
rm         = rm -f

.PHONY: clear_screen tests extend_cflags

$(BINDIR)/$(TARGET): $(OBJECTS) $(INCLUDES)
    $(LINKER) $(OBJECTS) $(LFLAGS) -o $@
    @echo -e "Linking complete!\n"

$(OBJECTS): $(OBJDIR)/%.o : $(SRCDIR)/%.cc $(INCLUDES)
    @mkdir -p $(OBJDIR) $(BINDIR)
    $(CC) $(CFLAGS) -c $< -o $@
    @echo -e "Compiled "$<" successfully!\n"

.PHONY: clean
clean:
    @$(rm) $(OBJECTS)
    @echo "Cleanup complete!"

.PHONY: remove
remove: clean
    @$(rm) $(BINDIR)/$(TARGET)
    @echo "Executable removed!"

clear_screen:
    @clear

extend_cflags:
    $(eval CFLAGS += $(DEBUG_MODE))

tests: | remove extend_cflags $(BINDIR)/$(TARGET) clear_screen
    @$(BINDIR)/$(TARGET)

Upvotes: -2

Ian Ooi
Ian Ooi

Reputation: 1703

Another answer is here: Define make variable at rule execution time.

For the lazy, you can have rules like the following (FLAG and DEBUG are my variables):

.DBG:
    $(eval FLAG += $(DEBUG))

Upvotes: 56

Beta
Beta

Reputation: 99164

Yes, there is an easy way to do it, and without rerunning Make. Use a target-specific variable value:

test: clean debug_compile

debug_compile: ERLCFLAGS += -DTEST
debug_compile: compile compile_test;

Upvotes: 105

Didier Trosset
Didier Trosset

Reputation: 37477

Edit: As explained by Beta in the other answer, it is possible.

No. There is no way to do this in the Makefile. You can however change the value of a variable on the make command line. If you rewrite your Makefile as follows:

ERLCFLAGS += $(ERLCFLAGSADDED)

%.erl: %.beam
    $(ERLC) $(ERLCFLAGS) -o ebin $<

test: clean compile compile_test

Then, you can invoke make to perform your tests using:

make ERLCFLAGSADDED=-DTEST test

Upvotes: -10

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