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Reputation: 5022

Implementing delay in VHDL state machine

I'm writing a state machine which controls data flow from a chip by setting and reading read/write enables. My clock is running at 27 MHz giving a period of 37 ns. However the specification for the chip I'm communicating with requires I hold my 'read request' signal for at least 50 ns. Of course this isn't possible to do in one cycle since my period is 37 ns.

I have considered I could create an additional state which does nothing but flag the next state to be the one I actually complete the read on, hence adding another period delay (meaning I hold 'read request' for 74 ns), but this doesn't sound like good practice.

The other option is perhaps to use a counter, but I wonder if there's perhaps yet another option I haven't visited yet?

How should one implement delay in a state machine when a state should last longer than one clock period?

Thanks!

T1 must be greater than 50 ns (T1 must be greater than 50 ns) Please see here for the full datasheet.

Upvotes: 0

Views: 1622

Answers (1)

Martin Thompson
Martin Thompson

Reputation: 16792

Delays are only reliably doable using the clock - adding an extra "tick" either via an extra state or using a counter in the existing state is perfectly acceptable to my mind. The counter has the possibility of being more flexible if you re-use the same state machine with a slower external chip (or if you use a different clock frequency to feed the FPGA) - you can just change the maximum count, instead of adding multiple "wait" states to the state machine.

Upvotes: 1

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