StackOverflow Questions for Tag: vhdl

Jamari

Reputation: 1

What's the difference between a constant and an inline constant in Vivado?

vhdlfpgavivadointel-fpga

Score: 0

Answers: 0

zipeilu

Reputation: 1

Using Finite State Machine model to design LCD1602 driver in VHDL

vhdlfpga

Score: -4

Answers: 1

FalconS

Reputation: 9

Signed Fixed-Point Multiplier in VHDL || Looking for Optimization or alternative approach

signal-processingvhdlfpgahdlfixed-point

Score: 0

Answers: 0

Manchineel

Reputation: 355

Vivado: Differing behavior between Behavioral and Post-Synthesis Functional Simulation

vhdlvivado

Score: 1

Answers: 0

Q-Tip

Reputation: 113

VHDL Generic number concatenation of std_logic_vector

vhdl

Score: 1

Answers: 1

Mustafa Guler

Reputation: 1

2 unit communication with Multi Gigabit Transceiver via SFP connector

vhdlfibers

Score: -3

Answers: 0

trican

Reputation: 1195

Fast, small area and low latency partial sorting algorithm

algorithmsortingvhdlverilogfpga

Score: 8

Answers: 6

Антон Козлов

Reputation: 1

Statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition(vhdl)

vhdl

Score: -3

Answers: 1

Aaron Linnell

Reputation: 152

Why is an array whose elements are arrays with non-identical ranges not allowed, even if all indices and values are constants?

vhdlvhdl-2008

Score: 0

Answers: 0

Jim Clay

Reputation: 119

Variable length unsigned in VHDL function

vhdlxilinx-ise

Score: 0

Answers: 1

Antonius Florea

Reputation: 11

Why does my Mealy FSM written in VHDL get stuck in the wrong state at the end?

vhdlxilinxvivadofsm

Score: 1

Answers: 1

Yassin Atwa

Reputation: 7

No signals using library ieee_proposed using Newton-Raphson refinement

floating-pointvhdlvivado

Score: -1

Answers: 1

pat._

Reputation: 51

How does the signal value change if it's own value is used to calculate it?

concurrencyarchitecturesignalsvhdlhdl

Score: 1

Answers: 1

FritzDC

Reputation: 507

Real-life use of SLA operator in VHDL

vhdl

Score: 5

Answers: 2

VHDL Addict

Reputation: 171

What does 1-, 2-, or 3-process mean for an FSM in VHDL?

coding-stylevhdlfsm

Score: 8

Answers: 4

A. Kieffer

Reputation: 372

Procedure call through different packages in VHDL

vhdl

Score: 1

Answers: 1

Bimo

Reputation: 6647

In VHDL, assigning a 2D array of std_logic using initialization array of integers... (slv_2dim, sls_2dim, slu_2dim)

vhdlvhdl-2008

Score: 1

Answers: 2

aschipfl

Reputation: 34979

How to form a Qualified Expression of an Array Type with a Single Element?

vhdl

Score: 0

Answers: 1

Sofía Acuña

Reputation: 27

Constant expression required width mismatch in assignment. Non synthesizable VHDL code line

floating-pointvhdl

Score: 0

Answers: 1

detly

Reputation: 30342

Why not a two-process state machine in VHDL?

vhdlidiomsfsm

Score: 6

Answers: 4

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StackOverflow Questions for Tag: vhdl

What&#39;s the difference between a constant and an inline constant in Vivado?

Using Finite State Machine model to design LCD1602 driver in VHDL

Signed Fixed-Point Multiplier in VHDL || Looking for Optimization or alternative approach

Vivado: Differing behavior between Behavioral and Post-Synthesis Functional Simulation

VHDL Generic number concatenation of std_logic_vector

2 unit communication with Multi Gigabit Transceiver via SFP connector

Fast, small area and low latency partial sorting algorithm

Statement is not synthesizable since it does not hold its value under NOT(clock-edge) condition(vhdl)

Why is an array whose elements are arrays with non-identical ranges not allowed, even if all indices and values are constants?

Variable length unsigned in VHDL function

Why does my Mealy FSM written in VHDL get stuck in the wrong state at the end?

No signals using library ieee_proposed using Newton-Raphson refinement

How does the signal value change if it&#39;s own value is used to calculate it?

Real-life use of SLA operator in VHDL

What does 1-, 2-, or 3-process mean for an FSM in VHDL?

Procedure call through different packages in VHDL

In VHDL, assigning a 2D array of std_logic using initialization array of integers... (slv_2dim, sls_2dim, slu_2dim)

How to form a Qualified Expression of an Array Type with a Single Element?

Constant expression required width mismatch in assignment. Non synthesizable VHDL code line

Why not a two-process state machine in VHDL?

What's the difference between a constant and an inline constant in Vivado?

How does the signal value change if it's own value is used to calculate it?