StackOverflow Questions for Tag: verilog

Dev Munvar

Reputation: 13

Trying to use different baud rates for this UART program in EDA Playground

verilogfpgauartbaud-rateedaplayground

Score: 0

Answers: 0

pbandlead

Reputation: 21

CocoTB: How to test interaction between two Verilog modules

pythonverilogsystem-veriloghdlcocotb

Score: 1

Answers: 1

dhodul

Reputation: 43

Issue with driving an LED matrix using an FPGA (Verilog)

verilogfpgahdlled

Score: 4

Answers: 2

Subramanya Krishna

Reputation: 175

How to write a part select expression using shift operator in system verilog?

verilogsystem-verilog

Score: 0

Answers: 1

Sharmila Palli

Reputation: 11

Synchronous FIFO

verilogsynchronousfifo

Score: -3

Answers: 0

Sharmila Palli

Reputation: 11

Default value of wire is Z, but in first instantiation it is taking 0. How this is possible?

verilogsystem-verilog

Score: 1

Answers: 1

AVAV

Reputation: 11

Code error: near "" gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class

verilogsystem-verilog

Score: 0

Answers: 1

his_dudeness

Reputation: 43

The number symbol in Verilog

verilogfpga

Score: 0

Answers: 1

Neela Lohith

Reputation: 21

How to initialise a register to a random value in verilog?

verilogsystem-verilog

Score: 1

Answers: 4

user1978273

Reputation: 514

repetition operator in systemverilog

verilogsystem-verilog

Score: 2

Answers: 1

tr1umph

Reputation: 23

How to fix multiple driver and combinational loop problems?

verilogsystem-veriloghdlregister-transfer-level

Score: 1

Answers: 1

Paulo

Reputation: 135

Why does carry disappear in addition?

verilogsystem-veriloghardwaredigital

Score: 1

Answers: 1

FPGAguru2015

Reputation: 23

FSM stuck at one state

verilogsystem-verilogfsm

Score: -1

Answers: 1

sirblobfish

Reputation: 83

Signed multiplication: multiplying numbers of different sizes?

verilogsystem-verilog

Score: 8

Answers: 1

Meir

Reputation: 307

verilog LRM 23.3.3.1 connecting output to output

verilogsystem-verilogiverilog

Score: 1

Answers: 2

Sean Sandler

Reputation: 1

How to create a verilog testbench

verilogsystem-verilogtest-bench

Score: -1

Answers: 0

foobarfuzzbizz

Reputation: 58705

Does Verilog support short circuit evaluation?

verilog

Score: 5

Answers: 2

trican

Reputation: 1195

Fast, small area and low latency partial sorting algorithm

algorithmsortingvhdlverilogfpga

Score: 8

Answers: 6

omar sweiss

Reputation: 1

Interface port must be passed an actual interface error

verilogsystem-verilogverificationuvmquestasim

Score: -1

Answers: 0

Dev Munvar

Reputation: 13

Why does APB testbench not send data into the prdata register?

verilogsystem-veriloguvmtest-benchedaplayground

Score: 1

Answers: 1

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StackOverflow Questions for Tag: verilog

Trying to use different baud rates for this UART program in EDA Playground

CocoTB: How to test interaction between two Verilog modules

Issue with driving an LED matrix using an FPGA (Verilog)

How to write a part select expression using shift operator in system verilog?

Synchronous FIFO

Default value of wire is Z, but in first instantiation it is taking 0. How this is possible?

Code error: near &quot;&quot; gmii_interface&quot;: Syntax error, unexpected IDENTIFIER, expecting class

The number symbol in Verilog

How to initialise a register to a random value in verilog?

repetition operator in systemverilog

How to fix multiple driver and combinational loop problems?

Why does carry disappear in addition?

FSM stuck at one state

Signed multiplication: multiplying numbers of different sizes?

verilog LRM 23.3.3.1 connecting output to output

How to create a verilog testbench

Does Verilog support short circuit evaluation?

Fast, small area and low latency partial sorting algorithm

Interface port must be passed an actual interface error

Why does APB testbench not send data into the prdata register?

Code error: near "" gmii_interface": Syntax error, unexpected IDENTIFIER, expecting class