Reputation: 43
Can anyone please tell me what is the meaning of "#" sign in Verilog?
For instance:
counter <= #1 counterNext;
Upvotes: 0
Views: 1050
Reputation: 62163
#
is for a delay. #1
adds a delay of one time unit. This is defined in the free IEEE Std 1800-2012 document in the "Procedural timing controls" section.
Upvotes: 1