CODEWITHSUNDEEP
verilog
user292965
user292965

Reputation: 163

What is >>>symbol in verilog?

May I know what is this symbol >>> in verilog. When should I use it? Thanks!

e.g 

always @(posedge Clock) begin
  if (Clear) begin
    a < = c>>>8;
    b < = d>>>16;
  end
end

Upvotes: 4

Views: 5416

Answers (1)

Ian
Ian

Reputation: 30813

It is an arithmetic right shift operator (see page 19-20 of the link). It is the reverse case from Java (Java >> is arithmetic right shift, while >>> is logical right shift).

Arithmetic right shift is to handle case when the number right-shifted is positive/negative with this behavior:

Shift right specified number of bits, fill with value of sign bit if expression is signed, othewise fill with zero

To illustrate, if you have signed expression with value of, say like this:

1000 1100 
--------- >>> 2
1110 0011 //note the left most bits are 1

But for unsigned:

1000 1100 
--------- >>> 2
0010 0011

The left most will be filled with 0.

Upvotes: 6

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