CODEWITHSUNDEEP
verilog
Michael Ochs
Michael Ochs

Reputation: 2870

Verilog: Setting a constant value on clock even

I am new to Verilog, so this question might be quite dumb.

What I am trying: I have a component that has a clk, an 8 bit input and an 8 bit output. What it should do, is:

If the clock event is negative edge, it should set the output to 0 If the clock event is positive edge, it should set the output to whatever input is at this moment of the edge event. During the high phase of the clock, the output should NOT change, regardless changes on the input.

What I tried so far:

always @(negedge clk)
    _ledOut <= 0;

always @(posedge clk)
    _ledOut[RowSize-1:0] <= ledIn[RowSize-1:0];

This tells my, that it can't resolve multiple constant drivers for net _ledOut.

However, putting this together in an always @(negedge clk, posedge clk) tells me, it can't test for both conditions.

So I tried to make just one always @(clk) block and then used an if statement:

always @(clk) begin
    if(clk == 0)
        _ledOut <= 0;
    else if(clk == 1)
        _ledOut[RowSize-1:0] <= ledIn[RowSize-1:0];
end

But this didn't just switch on a clk event. During the high phase of the clock, it links _ledOut with ledIn, so that changes on ledIn do also have effect on _ledOut. What am I doing wrong here?

Best regards, Michael

Upvotes: 2

Views: 4172

Answers (4)

toolic
toolic

Reputation: 61977

Consider the following stimulus:

module tb;

parameter RowSize = 8;
reg clk;
reg [7:0] ledIn, _ledOut;

always @(clk) begin
    if(clk == 0)
        _ledOut <= 0;
    else if(clk == 1)
        _ledOut[RowSize-1:0] <= ledIn[RowSize-1:0];
end

initial begin
    $monitor($time, " clk=%b ledIn=%h _ledOut=%h", clk, ledIn, _ledOut);
    ledIn = 0;
    #22 ledIn = 8'h55;
    #20 $finish;
end

always begin
    #5 clk <= 0;
    #5 clk <= 1;
end

endmodule

It produces this output:

               0 clk=x ledIn=00 _ledOut=xx
               5 clk=0 ledIn=00 _ledOut=00
              10 clk=1 ledIn=00 _ledOut=00
              15 clk=0 ledIn=00 _ledOut=00
              20 clk=1 ledIn=00 _ledOut=00
              22 clk=1 ledIn=55 _ledOut=00
              25 clk=0 ledIn=55 _ledOut=00
              30 clk=1 ledIn=55 _ledOut=55
              35 clk=0 ledIn=55 _ledOut=00
              40 clk=1 ledIn=55 _ledOut=55

Notice at time 22, when ledIn changes, the _ledOut output does not change. _ledOut only changes at the next posedge of clk at time 30. Therefore, the always @(clk) solution is doing what you want: the output only changes at the clock edge, as you specified.

Upvotes: 1

shuckc
shuckc

Reputation: 2994

This is a pretty unusual question, and it makes me advise you need to give more information about what you are actually trying to achieve, since it may well impact the timing performance and clock constraints if this is targeting an FPGA. Synthesis has been mentioned, but what will you be feeding the clock-gated output into? If it's a pin-pad, then you should read the DDR pad buffers in the device specifications and infer the specific primitive to be able to drive a DDR signal.

If you are keeping this signal within the chip then this is a very bizarre request. If I needed to generate that waveform, I would probably use a PLL to generate a phase-locked clock at twice the base frequency and put the gated data into that domain, with a toggle to apply the mast, so that the tooling will be able to properly analyse the clock crossings and the resulting data path is still effectively transitioning on a single edge.

The answers above to infer a register with a combinatorial multiplexer forced on the output is interesting, but whatever you feed this into will have to deal with awkward setup/hold conditions, and if on-chip, would only be sampling one edge anyway, so this is kind of redundant.

Upvotes: 0

Michael Ochs
Michael Ochs

Reputation: 2870

Ok, here is my working solution now. Maybe it's not the best verilog code you have seen out there. ;) This is, however, my first thing I do with it, as a project at my university. So as long as it does what I want it to do, this is a great success to me! ;)

Here is the code I used now, thanks to Adam12:

parameter RowSize = 8;

input clk;
input [RowSize-1:0] ledIn;
output [RowSize-1:0] ledOut;

reg[RowSize-1:0] _ledOut;
assign ledOut = _ledOut & {RowSize{clk}};

always @(posedge clk) begin
    _ledOut[RowSize-1:0] <= ledIn[RowSize-1:0];
end

Upvotes: 1

user597225
user597225

Reputation:

This tells my, that it can't resolve multiple constant drivers for net _ledOut.

For synthesis you cannot assign reg types from multiple always blocks.

However, putting this together in an always @(negedge clk, posedge clk) tells me, it can't test for both conditions.

This essentially describes a DDR register. While many FPGA devices have these they typically cannot be synthesized. Xilinx uses ODDR2 and IDDR2 primitives if you really need this functionality.

If the clock event is negative edge, it should set the output to 0 If the clock event is positive edge, it should set the output to whatever input is at this moment of the edge event. During the high phase of the clock, the output should NOT change, regardless changes on the input.

If this is all you need then you can use a D flip flop with an AND gate on the output. The flip-flop will sample ledIn on each rising edge of clk and the AND gate will mask the output whenever the clock is zero. This is not ideal as you generally do not want clocks to touch non-sequential logic but avoiding this would likely mean changing your requirements.

As toolic indicated, the code you posted will work but you should understand that code will synthesize to a multiplexer controlled by clk.

Upvotes: 5

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