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vhdlverilog
Brandon J
Brandon J

Reputation: 51

Verilog equivalent of time type constant

Is there a Verilog equivalent of the following statement in VHDL? I have some generic ports that require time values

constant TIME_C : time := 10 ms;

I tried this as a guess, but it failed syntax. 

localparam TIME_C = 10 ms;

'ms' doesn't appear to be a reserved keyword in Verilog, but my IDE's editor highlights it blue, so I'm thinking maybe there is a way...

Upvotes: 0

Views: 2309

Answers (1)

dwikle
dwikle

Reputation: 6978

You can do this:

`timescale 1ms/1ms

module foo();
  localparam TIME_C = 10;
  ...
endmodule

In Verilog, it is important to understand that variables or constants representing times are simply numerical values without any context. The timescale of the current module is what determines how the value is interpreted. In the example code above, #TIME_C will create a delay of 10ms because TIME_C equals 10 and the timescale is 1ms.

If you have to feed a time value to a port of a module, make sure you know what the timescale of the module is (if specified).

FYI, SystemVerilog added a few features related to specifying times and timescales.

Upvotes: 2

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