CODEWITHSUNDEEP
vhdlverilog
Rudy01
Rudy01

Reputation: 1087

VHDL constant used in Verilog

I have defined a VHDL constant, which I use as a switch inside a "generate" statement to whether generate a portion of the code or skip it. I have a Verilog module in the same top level, and I would like to do something similar. I want to use the VHDL constant in Verilog's "ifdef" statement, to either instantiate or skip the Verilog module. Is there any tricks that I can play to achieve this? Since I know that VHDL constants cannot be used in Verilog "ifdef" statements.

Thanks, --Rudy

Upvotes: 2

Views: 1149

Answers (1)

Greg
Greg

Reputation: 19122

The `ifdef would mean you need to decide when and if to set various `define MY_MACRO_DEF and can pollute your global name space and is compiling order dependent.

Instead, use Verilog's generate, introduced in IEEE Std 1364-2001. It is similar to VHDLs approach to generate. Here is an example:

module my_module #(parameter PARAM_VALUE=0) ( /* ports */ );
  generate
    if (PARAM_VALUE==1) begin
     ThisModule subinst ( .* );
    else begin
      ThatMoudle subinst ( .* );
    end
  endgenerate
endmodule

module top;
  /* nets */
  genvar gvar_i;
  generate
    for (gvar_i = 0; gvar_i<2; gvar_i=gvar_i+1) begin
      my_module #(.PARAM_VALUE(gvar_i)) inst ( .* );
    end
  endgenerate
endmodule
  • IEEE Std 1364-2001 § 12.1.3 Generated instantiation
  • IEEE Std 1364-2005 § 12.4 Generate constructs
  • IEEE Std 1800-2012 (SystemVerilog) § 27. Generate constructs

Upvotes: 2

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