Which data type in verilog is equivalent to "variable" in VHDL?

Question

How do I write equivalent verilog code for the below VHDL code? I show my verilog code behind the VHDL code. The verilog code does compile, but aux is invalid during the entire simulation.

VHDL: (classic_multiplier_parameters.vhd defines m = 8)

library ieee; 
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.classic_multiplier_parameters.all;

entity poly_multiplier is
port (
  a, b: in std_logic_vector(M-1 downto 0);
  d: out std_logic_vector(2*M-2 downto 0)
);
end poly_multiplier;


architecture simple of poly_multiplier is
  type matrix_ands is array (0 to 2*M-2) of STD_LOGIC_VECTOR(2*M-2 downto 0);
  signal a_by_b: matrix_ands;
  signal c: std_logic_vector(2*M-2 downto 0);
begin

  gen_ands: for k in 0 to M-1 generate
    l1: for i in 0 to k generate
       a_by_b(k)(i) <= A(i) and B(k-i);
    end generate;
  end generate;

  gen_ands2: for k in M to 2*M-2 generate
    l2: for i in k to 2*M-2 generate
       a_by_b(k)(i) <= A(k-i+(M-1)) and B(i-(M-1));
    end generate;
  end generate;

  d(0) <= a_by_b(0)(0);
  gen_xors: for k in 1 to 2*M-2 generate
    l3: process(a_by_b(k),c(k)) 
        variable aux: std_logic;
        begin
        if (k < M) then
          aux := a_by_b(k)(0);
          for i in 1 to k loop aux := a_by_b(k)(i) xor aux; end loop;
        else
          aux := a_by_b(k)(k);
          for i in k+1 to 2*M-2 loop aux := a_by_b(k)(i) xor aux; end loop;
        end if;
        d(k) <= aux;
    end process;
  end generate;

end simple;

Verilog:

module mul(
    a, b,
    d);
parameter M = 8;

input [M-1:0] a, b;
output [2*M-2:0] d;

wire [2*M-2:0] a_by_b [2*M-2:0];
wire aux;
//`UNPACK_ARRAY(2*M-2, 2*M-2, pack_a_by_b, a_by_b)

    //the first and
    genvar i, k;
    generate 
    for(k=0; k<=M-1; k=k+1) begin: for1_outer
        for(i=0; i<=k; i=i+1) begin: for1_inner
            assign a_by_b[k][i] = a[i] & b[k-i];
        end
    end
    endgenerate

    //second and
    generate 
    for(k=M; k<=2*M-2; k=k+1) begin: for2_outer
        for(i=k; i<=2*M-2; i=i+1) begin: for2_inner
            assign a_by_b[k][i] = a[k-i+(M-1)] & b[i-(M-1)];
        end 
    end
    endgenerate

    assign d[0] = a_by_b[0][0];
    // xors
    generate
    for(k=1; k<=2*M-2; k=k+1) begin: for3_outer
        if(k < M) begin
            assign aux = a_by_b[k][0];
            for(i=1; i<=k; i=i+1) begin: for3_inner1
                assign aux = a_by_b[k][i] ^ aux;
            end
        end
        else begin
            assign aux = a_by_b[k][k];
            for(i=k+1; i<=2*M-2; i=i+1) begin: for3_inner2
                assign aux = a_by_b[k][i] ^ aux;
            end
        end
        assign d[k] = aux;
    end
    endgenerate
endmodule

Verilog: (aux as reg type)

module mul(
    a, b,
    d);
parameter M = 3;

input [M-1:0] a, b;
output [2*M-2:0] d;

wire [2*M-2:0] a_by_b [2*M-2:0];
reg aux = 1'b1;
//`UNPACK_ARRAY(2*M-2, 2*M-2, pack_a_by_b, a_by_b)

    //the first and
    genvar i, k;
    generate 
    for(k=0; k<=M-1; k=k+1) begin: for1_outer
        for(i=0; i<=k; i=i+1) begin: for1_inner
            assign a_by_b[k][i] = a[i] & b[k-i];
        end
    end
    endgenerate

    //second and
    generate 
    for(k=M; k<=2*M-2; k=k+1) begin: for2_outer
        for(i=k; i<=2*M-2; i=i+1) begin: for2_inner
            assign a_by_b[k][i] = a[k-i+(M-1)] & b[i-(M-1)];
        end 
    end
    endgenerate

    assign d[0] = a_by_b[0][0];
    // xors
    generate
    for(k=1; k<=2*M-2; k=k+1) begin: for3_outer
        if(k < M) begin
            always @(*) begin 
                aux = a_by_b[k][0];
            end
            for(i=1; i<=k; i=i+1) begin: for3_inner1

            always @(*) begin 
                aux <= a_by_b[k][i] ^ aux;
            end
            end
        end
        else begin

            always @(*) begin 
            aux <= a_by_b[k][k];
            end
            for(i=k+1; i<=2*M-2; i=i+1) begin: for3_inner2

            always @(*) begin 
                aux <= a_by_b[k][i] ^ aux;
            end
            end
        end
        assign d[k] = aux;
    end
    endgenerate
endmodule

Answer 1

Sounds like you are looking for "reg". So for instance, reg aux instead of wire aux, and get rid of the "assigns" when you assign it.

(That said, that doesn't seem to be the only problem with this code.)