CODEWITHSUNDEEP
veriloghdl
ivanovishado
ivanovishado

Reputation: 97

Is there a 'var' type in Verilog to store results?

I have this register in Verilog... I want to know if there's a way to store the result of WIDTH-1 in a var, so it doesn't repeat for every port.

Any other recomendation about my code is welcome!

module asynchronous_register(d, clk, reset, q);

parameter   WIDTH = 8;

input       [WIDTH-1:0] d;
input       clk;
input       reset;

output      [WIDTH-1:0] q;

reg         [WIDTH-1:0] q;

always @(posedge clk or negedge reset) begin
    case (reset)
        1'b1:       q <= d;
        default:    q <= 1'b0;
    endcase
end

endmodule

Upvotes: 0

Views: 81

Answers (1)

dave_59
dave_59

Reputation: 42788

The way to do this in Verilog is: 

 module asynchronous_register #(parameter WIDTH=8, localparam MSB=WIDTH-1) ( 
   input       [MSB:0] d,
   input       [MSB:0] clk,
   input       [MSB:0] reset,

   output reg  [MSB:0] q
  );
always @(posedge clk or negedge reset) begin
    case (reset)
        1'b1:       q <= d;
        default:    q <= 1'b0;
    endcase
end

endmodule

Upvotes: 1

Related Questions