CODEWITHSUNDEEP
veriloghdl
user3081612
user3081612

Reputation: 9

Verilog: Passing parameters

I have written two verilog modules. The first one is named topmodule.v and the second one is tx.v. The module topmodule.v pass a parameter data[31:0] to tx.v. I want to take the variables Rmax and Cmax from data[31:0]. After that I want to make Rmax and Cmax to be the width of a bus. Moreover, I want to define a reg matrix called Mat with dimensions Cmax-x-Rmax. I receive the error at the 6th line of the code, "Range must be bounded by constant expression". Kindly help me to resolve this problem. The code is given below.

tx (data, output)
input [31:0] data;
reg [15:0] Rmax, Cmax;
assign Rmax [15:0] = data [31:16];
assign Cmax [15:0] = data [15:0];
reg [Rmax-1:0] Matrix [0:Cmax-1];

Upvotes: 0

Views: 880

Answers (2)

nguthrie
nguthrie

Reputation: 2685

If you really want these to be parameters then use that:

module tx #(parameter DATA=32'h00000000) (
  // inputs and outputs here
  );

  reg [DATA[31:16]-1:0] Matrix [0:DATA[15:0]-1];

However, I'm not really sure of what you are trying to accomplish. Show some more pseudo code and get a more useful answer.

Upvotes: 0

Tim
Tim

Reputation: 35943

The error means pretty much what it says, you cannot have a variable size bus or array.

Declare your matrix to be the maximum size that you ever need, and if you want to use a smaller one, then just use a subsection of it while leaving the rest vacant.

Remember that the width of buses are physical objects, they can't change when the circuit is running, only during synthesis.

Upvotes: 2

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