StackOverflow Questions for Tag: hdl

pbandlead

Reputation: 21

CocoTB: How to test interaction between two Verilog modules

pythonverilogsystem-veriloghdlcocotb

Score: 1

Answers: 1

dhodul

Reputation: 43

Issue with driving an LED matrix using an FPGA (Verilog)

verilogfpgahdlled

Score: 4

Answers: 2

FalconS

Reputation: 9

Signed Fixed-Point Multiplier in VHDL || Looking for Optimization or alternative approach

signal-processingvhdlfpgahdlfixed-point

Score: 0

Answers: 0

tr1umph

Reputation: 23

How to fix multiple driver and combinational loop problems?

verilogsystem-veriloghdlregister-transfer-level

Score: 1

Answers: 1

MICHAEL MURITHI

Reputation: 1

D register not updating its value in CPU.hdl implementation in NAND2Tetris, regardless of load flag

cpu-architecturehdlnand2tetris

Score: -1

Answers: 0

Saeed Raffoul

Reputation: 31

What is meant by this SystemVerilog typedef enum statement?

system-veriloghdl

Score: 1

Answers: 2

correlator

Reputation: 9

Conway's Game of Life Verilog

veriloghdlconways-game-of-life

Score: 0

Answers: 0

pat._

Reputation: 51

How does the signal value change if it's own value is used to calculate it?

concurrencyarchitecturesignalsvhdlhdl

Score: 1

Answers: 1

fltray10

Reputation: 33

Bluespec Verilog - polymorphic vector type

architecturesystem-veriloghdlbluespec

Score: -1

Answers: 1

tamo

Reputation: 11

How can I transform yosys gate primitives (e.g. $reduce_or) to simple gates and then pattern match those to more complex Verilog cells?

veriloghdlsynthesisdigital-logicyosys

Score: 0

Answers: 0

MS Keane

Reputation: 31

Does Verilog automatically convert Behavioral modeling into Structural modeling?

veriloghdlsynthesis

Score: 3

Answers: 2

Jemimacakes

Reputation: 137

Verilog simulation: all outputs x

veriloghdl

Score: 1

Answers: 2

Antel

Reputation: 13

Error (10170): HDL syntax errors in Quartus (HDL)

verilogsystem-veriloghdlquartus

Score: 1

Answers: 1

Heinrich Mller Domtastick

Reputation: 1

8 way OR gate in Hack's HDL language

hdlnand2tetris

Score: 0

Answers: 1

D00MA

Reputation: 13

Errors in nand2tetris hardware simulator

hdlnand2tetris

Score: 0

Answers: 1

Tibio

Reputation: 23

Accessing Verilog genvar generated instances in simulation code

simulationveriloghdlsynthesis

Score: 2

Answers: 4

Louis Wascom

Reputation: 11

Writing recursive code to find unmatched parenthesis in a string?

recursionverilogsystem-veriloghdl

Score: 1

Answers: 3

Prerk

Reputation: 67

reg qb; cannot be driven by primitives or continuous assignment

veriloghdliverilog

Score: 1

Answers: 1

user9682193

Reputation: 1

Inverting pin value in physical constraints (Gowin EDA)

fpgahdl

Score: -1

Answers: 1

S1LV3R

Reputation: 135

Comparison error when implementing a MUX gate in nand2tetris

hdlhardwarenand2tetris

Score: 1

Answers: 2

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StackOverflow Questions for Tag: hdl

CocoTB: How to test interaction between two Verilog modules

Issue with driving an LED matrix using an FPGA (Verilog)

Signed Fixed-Point Multiplier in VHDL || Looking for Optimization or alternative approach

How to fix multiple driver and combinational loop problems?

D register not updating its value in CPU.hdl implementation in NAND2Tetris, regardless of load flag

What is meant by this SystemVerilog typedef enum statement?

Conway&#39;s Game of Life Verilog

How does the signal value change if it&#39;s own value is used to calculate it?

Bluespec Verilog - polymorphic vector type

How can I transform yosys gate primitives (e.g. $reduce_or) to simple gates and then pattern match those to more complex Verilog cells?

Does Verilog automatically convert Behavioral modeling into Structural modeling?

Verilog simulation: all outputs x

Error (10170): HDL syntax errors in Quartus (HDL)

8 way OR gate in Hack&#39;s HDL language

Errors in nand2tetris hardware simulator

Accessing Verilog genvar generated instances in simulation code

Writing recursive code to find unmatched parenthesis in a string?

reg qb; cannot be driven by primitives or continuous assignment

Inverting pin value in physical constraints (Gowin EDA)

Comparison error when implementing a MUX gate in nand2tetris

Conway's Game of Life Verilog

How does the signal value change if it's own value is used to calculate it?

8 way OR gate in Hack's HDL language