StackOverflow Questions for Tag: fpga

Stranger Rookie
Stranger Rookie

Reputation: 9

Signed Fixed-Point Multiplier in VHDL || Looking for Optimization or alternative approach

Score: 0

Views: 59

Answers: 0

Read More
his_dudeness
his_dudeness

Reputation: 43

The number symbol in Verilog

Score: 0

Views: 1050

Answers: 1

Read More
ammous yosra
ammous yosra

Reputation: 1

read& write from sdram (on board Arty S7-25) to FIFOs on BRAM without axi bus?

Score: -2

Views: 14

Answers: 0

Read More
G273_ab
G273_ab

Reputation: 1

Electric UI Hardware detection

Score: -4

Views: 34

Answers: 0

Read More
alpd4
alpd4

Reputation: 1

Devicetree "ranges" property on simple-bus

Score: -1

Views: 67

Answers: 0

Read More
trican
trican

Reputation: 1195

Fast, small area and low latency partial sorting algorithm

Score: 8

Views: 4798

Answers: 6

Read More
joda
joda

Reputation: 425

Vexriscv - implement ram as block ram

Score: 1

Views: 197

Answers: 1

Read More
Daniel Li
Daniel Li

Reputation: 1

Illegal Period, set by Block, claiming it is non-integer multiple of the system rate

Score: -1

Views: 23

Answers: 0

Read More
jel88
jel88

Reputation: 35

SystemVerilog intermediate top output signal

Score: 0

Views: 59

Answers: 2

Read More
Ananth K
Ananth K

Reputation: 11

TCL Script for Including Date and Time in Top Module of Design Sources in Vivado

Score: 0

Views: 57

Answers: 1

Read More
saman
saman

Reputation: 311

OpenCL Quartus Hardware Generation time consuming

Score: 0

Views: 79

Answers: 1

Read More
Sero
Sero

Reputation: 51

LED Sequence on Basys3 with Verilog

Score: 1

Views: 68

Answers: 1

Read More
RhinoECE
RhinoECE

Reputation: 43

Connecting output of 4-bit counter to Hex to 7-Seg decoder and creating testbench

Score: 0

Views: 1132

Answers: 1

Read More
Ilan Mermelstein
Ilan Mermelstein

Reputation: 27

Is it a bad practice to reset a variable in one model using a variable from another model?

Score: 1

Views: 46

Answers: 1

Read More
Nicholas Stone
Nicholas Stone

Reputation: 9

Verilog Daisy-Chained Ripple Counter in actual FPGA

Score: 0

Views: 50

Answers: 0

Read More
mravenca
mravenca

Reputation: 11

Newbie question about programming Altera Cyclone II in Quartus II

Score: 0

Views: 1341

Answers: 1

Read More
Florinlego
Florinlego

Reputation: 35

Binary - BCD convertor works in sim, but does not work on FPGA

Score: 1

Views: 49

Answers: 1

Read More
lVitaD
lVitaD

Reputation: 53

NEC Infrared Transmission Protocol in C lanc on Xilinx

Score: 0

Views: 49

Answers: 1

Read More
G Boggs
G Boggs

Reputation: 391

Errors with ISE iMPACT obtaining JTAG chain

Score: 1

Views: 1847

Answers: 0

Read More
user8879429
user8879429

Reputation: 9

How does a mips 5-stage pipeline cpu handle exception and soft interrupt?

Score: -1

Views: 1102

Answers: 1

Read More
PreviousPage 1Next