StackOverflow Questions for Tag: cpu-architecture

Murad Bashirli

Reputation: 21

Are additional opcodes in RISC-V instructions important?

assemblycpu-architectureriscvinstruction-set

Score: 1

Answers: 2

Manters

Reputation: 55

How to waste a few CPU cycles without causing any memory accesses

assemblyx86cpu-architectureinteltiming

Score: 1

Answers: 0

Chris Khater

Reputation: 1

how to build the libpfm4 library on windows, it is originally a unix lib but they mentioned that it supports windows

cperformanceshared-librariescpu-architectureintel-pmu

Score: 0

Answers: 0

Nan Xiao

Reputation: 17477

Why does multi-thread program still need lock when running on a single-core CPU?

cmultithreadingarmcpu-architecturelow-level

Score: 0

Answers: 0

Vladislav Kogan

Reputation: 758

Why std::find_if significantly accelerates function only on Intel CPUs?

c++performancex86stdcpu-architecture

Score: 6

Answers: 0

Zuchao Wang

Reputation: 19

In pipelined processor design, why register file read/write are performed in half cycle?

mipscpu-architecturecpu-registers

Score: 1

Answers: 1

ben liu

Reputation: 21

where is directory memory of dir controller of cache coherence protocol stored in real chip?

cachingcpu-architecturecpu-cachegem5mesi

Score: 1

Answers: 0

Kislay Arya

Reputation: 1

How does the ROB track instructions from multiple logical threads in a core?

multithreadingoperating-systemcpu-architecturecontext-switchspeculative-execution

Score: 0

Answers: 0

user2088790

Reputation:

How to use Fused Multiply-Add (FMA) instructions with SSE/AVX

cssecpu-architectureavxfma

Score: 48

Answers: 2

maxpenguin

Reputation: 5149

Floating point vs integer calculations on modern hardware

c++x86floating-pointx86-64cpu-architecture

Score: 132

Answers: 11

uriDium

Reputation: 13420

Should Interlocked.CompareExchange also a volatile variable?

c#cpu-architecturevolatilelock-freecompare-and-swap

Score: 3

Answers: 3

geza

Reputation: 29970

What can cause an AVX2 dot product to perform differently for different runs?

c++performancecpu-architectureavx2dot-product

Score: 8

Answers: 1

Pierre

Reputation: 35296

java.lang.Runtime.getRuntime().availableProcessors() : difference beween java 8 (ncpus=32) and java 11 (ncpus=1)

javaversioncpucpu-architecture

Score: 2

Answers: 1

Jogging Song

Reputation: 573

Why is im2col-based 2d-convolution more efficient than naive SIMD-accelerated 2d-convolution?

memoryfloating-pointconv-neural-networkcpu-architectureinstruction-set

Score: 6

Answers: 1

Izzo

Reputation: 4928

Are SIMD and VLIW instructions the same thing?

x86cpu-architecturesimdinstruction-setvliw

Score: 2

Answers: 2

yhgu2000

Reputation: 364

Why can't we have a safe ISA?

securitymemory-managementcpu-architectureinstruction-setmemory-safety

Score: 3

Answers: 3

MinecraftShamrock

Reputation: 3574

Which factors affect the needed compiler?

compilationoperating-systemcpucpu-architectureinstruction-set

Score: 3

Answers: 3

Bioheater

Reputation: 31

Can you disable AVX in deepfacelab?

pythoncpucpu-architectureavxdeep-fake

Score: 0

Answers: 1

JohnTortugo

Reputation: 6625

Automatically unrolling and outputting for C/C++ code

gccllvmcpu-architectureiccloop-unrolling

Score: 9

Answers: 2

botismarius

Reputation: 3045

Detecting architecture at compile time from MASM/MASM64

assemblyx86-64cpu-architecturemasmmasm32

Score: 9

Answers: 3

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StackOverflow Questions for Tag: cpu-architecture

Are additional opcodes in RISC-V instructions important?

How to waste a few CPU cycles without causing any memory accesses

how to build the libpfm4 library on windows, it is originally a unix lib but they mentioned that it supports windows

Why does multi-thread program still need lock when running on a single-core CPU?

Why std::find_if significantly accelerates function only on Intel CPUs?

In pipelined processor design, why register file read/write are performed in half cycle?

where is directory memory of dir controller of cache coherence protocol stored in real chip?

How does the ROB track instructions from multiple logical threads in a core?

How to use Fused Multiply-Add (FMA) instructions with SSE/AVX

Floating point vs integer calculations on modern hardware

Should Interlocked.CompareExchange also a volatile variable?

What can cause an AVX2 dot product to perform differently for different runs?

java.lang.Runtime.getRuntime().availableProcessors() : difference beween java 8 (ncpus=32) and java 11 (ncpus=1)

Why is im2col-based 2d-convolution more efficient than naive SIMD-accelerated 2d-convolution?

Are SIMD and VLIW instructions the same thing?

Why can&#39;t we have a safe ISA?

Which factors affect the needed compiler?

Can you disable AVX in deepfacelab?

Automatically unrolling and outputting for C/C++ code

Detecting architecture at compile time from MASM/MASM64

Why can't we have a safe ISA?