StackOverflow Questions for Tag: mesi

ben liu

Reputation: 21

where is directory memory of dir controller of cache coherence protocol stored in real chip?

cachingcpu-architecturecpu-cachegem5mesi

Score: 1

Answers: 0

pveentjer

Reputation: 11392

How do modern Intel x86 CPUs implement the total order over stores

x86intelcpu-architecturememory-barriersmesi

Score: 8

Answers: 2

Jonas Jacob Biermann

Reputation: 139

MESI Protocol State Transition if Index Bits are Same but Tags differ

cachingcomputer-sciencemesi

Score: 0

Answers: 1

ajp

Reputation: 2463

optimal to flush low-contention atomic from caches?

multithreadingcpu-architectureatomiccpu-cachemesi

Score: 3

Answers: 1

ran ranran

Reputation: 1

What will happen if the processor perform a read operation while the cache line is still in the store buffer of another processor

cachingconsistencymesi

Score: 0

Answers: 1

dtwang

Reputation: 1

Confusions about the state transition of MSI/MESI directory protocol in the book "A Primer on Memory Consistency and Cache Coherence, Second Edition"

cachingmesi

Score: 0

Answers: 1

Suriyaa MM

Reputation: 3

Why race condition occurs when hardware has ensured coherency

c++cachingshared-memoryrace-conditionmesi

Score: 0

Answers: 2

Einheri

Reputation: 985

With the MESI protocol, a write hit also stalls the processor, right?

cachingarchitecturemultiprocessingvhdlmesi

Score: 3

Answers: 1

User710

Reputation: 1

MESI: why we need write-miss to move from shared to modified

cpucpu-architecturecpu-cachemesi

Score: 0

Answers: 2

jkang

Reputation: 549

MOESI Protocol: What happens when Owned is dirty and other processors read the line in Shared?

cpu-architecturecpu-cachemesi

Score: 0

Answers: 2

Cosmos

Reputation: 135

What happens with the store "that lost race" to shared memory in x86 TSO memory model?

x86cpucpu-architecturememory-modelmesi

Score: -1

Answers: 1

Triassic

Reputation: 41

How CPUs Use the LOCK Prefix to Implement Cache Locking and ensure memory consistency

javavolatilecpu-cachememory-barriersmesi

Score: 4

Answers: 0

blonded04

Reputation: 503

How `memory_order_relaxed` is enough in TTAS spinlock for Arm64?

c++armmemory-barriersspinlockmesi

Score: 0

Answers: 1

k1r1t0

Reputation: 767

Can CPU load data from another CPU's cache using LOCK CMPXCHG instruction in x86?

x86cpu-architectureatomiccpu-cachemesi

Score: 0

Answers: 0

klezki

Reputation: 93

Invalidation of an Exclusive cache line

cpu-architecturecpu-cachememory-barriersmesi

Score: 2

Answers: 0

Megan Darcy

Reputation: 582

cache coherence - Why are some steps considered exclusive?

cachingcpu-architecturecpu-cachecpu-coresmesi

Score: 0

Answers: 0

pippo

Reputation: 53

Is it Possible for a Thread to Read Stale Data Due to CPU Core Switching in a Multi-threaded Environment?

multithreadingmesi

Score: 0

Answers: 1

Monte

Reputation: 39

Confusing "Memory Barrier Example 1" in 《Memory Barriers: a Hardware View for Software Hackers》？

cpu-cachememory-barrierslocklessmesi

Score: 1

Answers: 0

Los Geles

Reputation: 31

Does store buffer send read invalidate message or invalidate req message?

cpucpu-architecturemesi

Score: 3

Answers: 1

Weipeng

Reputation: 1554

How is message queue implemented in cache coherence protocol?

concurrencycpu-architecturecpu-cachememory-barriersmesi

Score: 1

Answers: 1

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StackOverflow Questions for Tag: mesi

where is directory memory of dir controller of cache coherence protocol stored in real chip?

How do modern Intel x86 CPUs implement the total order over stores

MESI Protocol State Transition if Index Bits are Same but Tags differ

optimal to flush low-contention atomic from caches?

What will happen if the processor perform a read operation while the cache line is still in the store buffer of another processor

Confusions about the state transition of MSI/MESI directory protocol in the book &quot;A Primer on Memory Consistency and Cache Coherence, Second Edition&quot;

Why race condition occurs when hardware has ensured coherency

With the MESI protocol, a write hit also stalls the processor, right?

MESI: why we need write-miss to move from shared to modified

MOESI Protocol: What happens when Owned is dirty and other processors read the line in Shared?

What happens with the store &quot;that lost race&quot; to shared memory in x86 TSO memory model?

How CPUs Use the LOCK Prefix to Implement Cache Locking and ensure memory consistency

How `memory_order_relaxed` is enough in TTAS spinlock for Arm64?

Can CPU load data from another CPU&#39;s cache using LOCK CMPXCHG instruction in x86?

Invalidation of an Exclusive cache line

cache coherence - Why are some steps considered exclusive?

Is it Possible for a Thread to Read Stale Data Due to CPU Core Switching in a Multi-threaded Environment?

Confusing &quot;Memory Barrier Example 1&quot; in 《Memory Barriers: a Hardware View for Software Hackers》？

Does store buffer send read invalidate message or invalidate req message?

How is message queue implemented in cache coherence protocol?

Confusions about the state transition of MSI/MESI directory protocol in the book "A Primer on Memory Consistency and Cache Coherence, Second Edition"

What happens with the store "that lost race" to shared memory in x86 TSO memory model?

Can CPU load data from another CPU's cache using LOCK CMPXCHG instruction in x86?

Confusing "Memory Barrier Example 1" in 《Memory Barriers: a Hardware View for Software Hackers》？