StackOverflow Questions for Tag: memory-barriers

wangloo

Reputation: 105

Is the isb necessary between modifying ttbr and flushing TLB?

linux-kernelarchitecturearm64memory-barriersarmv8

Score: 2

Answers: 1

Robxley

Reputation: 23

Proper Use of Atomics for an Asynchronous Iterator with Multiple Producers and Consumers in c++20

c++multithreadingc++20memory-barriersstdatomic

Score: 1

Answers: 1

anon

Reputation:

Memory barriers in userspace? (Linux, x86-64)

c++cmultithreadinglock-freememory-barriers

Score: 18

Answers: 9

Some Name

Reputation: 9540

Array based Lock-Free stack. Is full fence necessary?

javamultithreadingx86memory-barrierslock-free

Score: 2

Answers: 1

Pacopenguin

Reputation: 374

Preventing reordering of writes before atomic store

c++multithreadingatomicmemory-barriersstdatomic

Score: 0

Answers: 1

knivil

Reputation: 807

Which memory barriers do I need, to make the writes to image in thread A visible in Thread B?

arrayscmultithreadingmemory-barriers

Score: 0

Answers: 1

Aimin Huang

Reputation: 175

Understanding memory order relaxed in C++

c++concurrencyatomicmemory-barriers

Score: 7

Answers: 2

Alex V.

Reputation: 46

Write to same color attachment from multiple batches

vulkanmemory-barriers

Score: 0

Answers: 1

pveentjer

Reputation: 11392

How do modern Intel x86 CPUs implement the total order over stores

x86intelcpu-architecturememory-barriersmesi

Score: 8

Answers: 2

k1r1t0

Reputation: 767

What is Memory Ordering Nuke in Intel CPUs?

x86cpu-architectureintelmemory-barriersspeculative-execution

Score: 1

Answers: 0

song xs

Reputation: 81

Does gcc treat relaxed atomic operation as a Compiler-fence?

c++gccatomicmemory-barriersmemory-model

Score: 5

Answers: 1

Gilgamesz

Reputation: 5073

Atomicity of loads and stores on x86

c++x86cpu-architectureatomicmemory-barriers

Score: 38

Answers: 2

untitled

Reputation: 429

Will memory write be visible after sending an IPI on x86?

assemblyx86operating-systemmemory-barriersmsr

Score: 8

Answers: 3

ron burgundy

Reputation: 83

Are acquire-release semantics transitive across threads?

c++multithreadingconcurrencymemory-barriersstdatomic

Score: 1

Answers: 1

relatively_random

Reputation: 5166

How does the common 4 thread example for demonstrating sequential consistency work on a system with cache coherence?

c++atomicmemory-barrierslock-freestdatomic

Score: 0

Answers: 0

Dmytro Kostenko

Reputation: 235

Why Did LOCK-prefixed Instructions Become Preferred Over MFENCE for Memory Fences in the JVM on x86?

assemblyx86cpu-architecturememory-barriersinstruction-set

Score: 1

Answers: 0

Ervin Xie

Reputation: 13

Dequeued item exists but std::counting_semaphore::try_acquire() fails in single-consumer MPSC queue

c++memoryconcurrencymemory-barriers

Score: 1

Answers: 1

pveentjer

Reputation: 11392

ARMv8.3 meaning of rcpc

armcpu-architecturememory-barriersmemory-modelarmv8

Score: 7

Answers: 2

Dmytro Kostenko

Reputation: 235

How Does the Store Buffer Drain in x86 Architecture Work?

x86cpu-architectureintelmemory-barriersmemory-model

Score: 1

Answers: 0

Lantanar

Reputation: 35

How do I thread safely write a struct to memory?

linuxmultithreadingrustx86-64memory-barriers

Score: 0

Answers: 0

PreviousPage 1Next