CODEWITHSUNDEEP
cachingmesi
dtwang
dtwang

Reputation: 1

Confusions about the state transition of MSI/MESI directory protocol in the book "A Primer on Memory Consistency and Cache Coherence, Second Edition"

All questions come from the book "A Primer on Memory Consistency and Cache Coherence, Second Edition".

The first question comes from "Table 8.1: MSI directory protocol—cache controller" (p158).

Table

In this red box, why can a subsequent load instruction hit a cache block which marked SMAD. Which means that the following load instruction in the store-load instrcution pair will return the old value.

Upvotes: 0

Views: 58

Answers (1)

Erkmen
Erkmen

Reputation: 56

Depends.

You notified others that you are going to make a change in this cacheline, which means you know what you are going to change in this cacheline. Simply, you can't scream to others "Hey, i'm going to change this block" without any idea about the new value, since you are an engineer, not a politician. =)

If this later load request, wants to read the part of the cache line you won't change, there is no difference between S or SM^AD.

If this later load request, wants to read the part of the cache line you will change, if a cacheline is in SM^AD stated, that means you'll change a part of this cacheline, maybe all of it, you should know the data you'll change right? Cache took that part of data in the older store request. So you have the data you'll write. You can respond with data you are holding to change, to this new request.

But ofc order of the load-store sequence should be kept till cache. Cache shouldn't see a load-store sequence as a store-load. (If you can escape from wrong responses in LSU or somewhere, it is ok too)

Upvotes: 0

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