Reputation: 1
Under the context of MESI protocol and the introducing of store buffer and invalidation queue, a write operation to a variable can be temporarily stored in the store buffer waiting for the related cache line arrival. Then what will happen if another processor whats to perform a read operation? Will the read operation be blocked unless the wirte operation performed before be finished?
I know that the processor received the invalidation request has to guarantee that no extra MESI message can be sent until the invalidation has been performed.But what if the invalidation message has already been processed?
Upvotes: 0
Views: 25
Reputation: 56
It depends on the protocol you are using. Some protocols as AXI & ACE, doesn't let the same cacheline operation to start. In that case, you'll be sure if HartX receive a request about a cacheline from any other Hart, request of this other Hart has priority and AXI&ACE protocol explains the cases and what to do.
If you are trying to use a custom protocol, and a Hart which started an operation in a cacheline, all harts should see all requests including own requests. So any Hart can decide which request is prioritized by arbitration logic of bus.
I guess you are trying to implement some custom protocol.
In your case, behaviour of HartX which started invalidation, depends on which request recieved first by HartX.
Case 1: If HartX sent an invalidation, and HartX receives a read request from any other hart before recieve its own invalidation request, it should respond this request with the data it didn't change, not with the data it'll write.
Case2: If HartX sent an invalidation, and HartX receives its own invalidation request. After that HartX receives a read request from any other hart, HartX should wait the up to date data and after got it should does write operation, then should respond that read request with the written data.
Upvotes: 0