CODEWITHSUNDEEP
verilogsystem-verilogfpgasynthesisasic
jel88
jel88

Reputation: 35

SystemVerilog intermediate top output signal

I am wondering which SystemVerilog coding fits better for ASIC/FPGA Synthesis/linting. I mean for simulation/synthesis/... purpose if it makes any difference and if a coding style is preferred, for example for a lot of signals, maybe passing by intermediate signals may slow down simulation ? For example, will the code cause a problem for design synthesis.

  1. Using intermediate signal
module top(output o);
  logic       o_sig ;
  sub i_sub (
      .i(),
      .o(o_sig) 
      );
  assign o = o_sig;
endmodule
  1. Direct connection
module top(output o);
  sub i_sub (
      .i(),
      .o(o) 
      );
endmodule

Upvotes: 0

Views: 59

Answers (2)

dave_59
dave_59

Reputation: 42698

For synthesis, they are logically equivalent. For both simulation and synthesis, optimization usually takes care of passing signals through ports or signal renaming from a continuous assignment. However, the direct connection is certainly less typing and less chance for typos. Also, assign statements do not pass strength information which might be needed for pull-up/down circuitry.

If you are just looking to have external port names that are different from the internal names, you can use a SystemVerilog alias

module top(output o);
  alias o_sig = o;
  sub i_sub (
      .i(),
      .o(o_sig) 
      );
endmodule

Or use a Verilog port expression:

module top(output .o(o_sig));
  logic       o_sig ;
  sub i_sub (
      .i(),
      .o(o_sig) 
      );
endmodule

Upvotes: 1

toolic
toolic

Reputation: 62163

Prefer the "Direct connection" in this case. There should be no difference with respect to synthesis.

There is no compelling reason to use the additional code (signal plus assign statement) in the "intermediate signal" case. This really just adds clutter, and if you do this for all signals, you could start to degrade simulation performance.

Upvotes: 1

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