CODEWITHSUNDEEP
veriloghdl
Jemimacakes
Jemimacakes

Reputation: 137

Verilog simulation: all outputs x

When I run my module through a simulator, my outputs are always all x.

Here is my code:

module state_machine(
    input clk_i,
    input reset_n,
    input LB,
    input RB,
    
    output reg [3:0] outputs
        );    

        reg [3:0] state;
        reg [3:0] state_n;          
        
        parameter FW = 4'b0101;
        parameter BWL = 4'b0000;
        parameter BWR = 4'b0000;
        parameter SL = 4'b0001;
        parameter SR = 4'b0100;     
    
        always @ (posedge clk_i, negedge reset_n)
            begin
                if(!reset_n)
                    state <= FW;
                else
                    state <= state_n;
            end      
     
        always @ (*)
            begin
                case(state)
                    FW: begin
                            if(!RB)
                                state_n = BWR;
                            else if(!LB)
                                state_n = BWL;
                        end
                    BWL: state_n = SL;
                    BWR: state_n = SR;
                    SL: state_n = FW;
                    SR: state_n = FW;
                    
                    default: state_n = FW;
                endcase
            end             
            
        always @ (*)
            begin
                outputs = state;
            end
endmodule

The clk_i input is a slowed clock made using a counter method, which is here:

module clock_counter(
    input clk_i,
    input reset_n,
    
    output reg clk_o
        );
    
        reg [19:0] count;

        always @ (posedge clk_i, negedge reset_n)
            begin
                count <= count + 1;
                if(!reset_n)
                    begin
                        clk_o <= 0;
                        count <= 0;
                    end
                else if(count >= 1039999)
                    begin
                        clk_o <= ~clk_o;
                        count <= 0;
                    end
            end

endmodule

They are both instantiated by a top module which does only that. I don't receive any errors, but I do get a few warnings about certain things I don't recognize being stuck at zero.

Can anyone see what is wrong?

Here is my testbench code:

    `timescale 1 ns / 1 ns

// Define Module for Test Fixture
module top_module_tf();

// Inputs
    reg reset_n;
    reg LB;
    reg RB;    

// Outputs
    wire [3:0] outputs;    

// Instantiate the UUT
    top_module UUT (
        .reset_n(reset_n), 
        .LB(LB), 
        .RB(RB), 
        .outputs(outputs)
        );    

// Initialize Inputs
    initial begin
            reset_n = 1; LB = 1; RB = 0;
 #500000000 reset_n = 1; LB = 1; RB = 1;
    end

endmodule // top_module_tf

Upvotes: 1

Views: 11570

Answers (2)

toolic
toolic

Reputation: 62236

You need to set your testbench reset_n signal to 0 at time 0 to reset your logic. After a delay, you should set reset_n to 1.

Change:

        reset_n = 1; LB = 1; RB = 0;

to:

        reset_n = 0; LB = 1; RB = 0;

All reg signals default to X.

Upvotes: 0

Will
Will

Reputation: 845

Using a reset is the traditional way to do it, but you could also give registers an initial value like this

reg LB = 1'b0;
reg RB = 1'b0;

Modelsim supports this, and quartus will synthesize reigsters which load the given value at startup. You can also do this in verilog 2001 port declarations

module some_module(  
  input wire clk,
  output reg[15:0] counter_val = 16'd12345,
  output wire some_other_signal);

So that is how you cut down on the amount of reset code you need for simulation. You need to think carefully before you get rid of resets though, e.g. make sure your logic will eventually roll around to valid states if your registers get corrupted.

Upvotes: -1

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