CODEWITHSUNDEEP
veriloghdl
a220599
a220599

Reputation: 39

Regarding verilog always blocks

I have an always block that looks like this

reg [31:0] r1;

always @(posedge clk)
  if(condition) begin
    r1<=32'hcafecafe;
  end

what happens to r1 when the condition is false? What does it get synthesized to ?

Upvotes: 0

Views: 230

Answers (3)

dave_59
dave_59

Reputation: 42673

I believe a synthesis tool treat this the same as

reg [31:0] r1 =32'h????????;

always @(posedge clk)
  if(condition)
    r1<=32'hcafecafe;
  else
   r1 <= r1;

Since the initial value is a don't care, the only other possible value is 32'hcafecafe, do the synthesis tool is free to synthesize it to a constant value.

Upvotes: 0

Rgarg
Rgarg

Reputation: 506

The problem here is you have not set any reset condition. Your code says if condition is true, r1 should be 32'hcafecafe. If you think about it carefully, if r1 is fixed to 32'hcafecafe, the tool is accomplishing what you have told it to do.

The correct code would be something like this:

reg [31:0] r1;

always @(posedge clk)
  if (sync_reset_b == 1) //synchronous reset
      r1<=32'h0; // or whatever you want it to be.
  else if(condition) begin
    r1<=32'hcafecafe;
  end

Upvotes: 1

Matthew
Matthew

Reputation: 13967

I tried two different synthesisers and both synthesised your code to 

reg [31:0] r1 = 32'hcafecafe;

This is not what I would have expected, because this code does not behave in exactly the same way as your RTL. In your RTL, r1 will be unknown until the first clock edge with condition high whereupon it will take the value 32'hcafecafe. The synthesised output will already have the value 32'hcafecafe before that first clock edge. I would have expected the synthesiser output to be 32 enabled D-type flip-flops with their inputs tied to 32'hcafecafe.

Upvotes: 0

Related Questions