CODEWITHSUNDEEP
verilog
user1491918
user1491918

Reputation: 31

Verilog always block

I just want to use some if else statement in verilog. So I have to use always block.

integer count,index;
reg a=0;
always@(a) begin
   a=1;
   for(count=0;count<7;count=count+1) begin
      index=4*count;
      if((significand[index]==1'b0)&&(significand[index+1]==1'b0)&&
     (significand[ind‌​ex+2]==1'b0) &&(significand[index+3]==1'b0))
    lzero=lzero+1;
   end
end

This code does make some sense now. I was able to get the correct simulation result, but I failed to get the correct synthesis on the board. Please help

Upvotes: 0

Views: 7300

Answers (2)

FarhadA
FarhadA

Reputation: 883

This is a very typical problem with people who know how to program in C or C++ but forget that Verilog and VHDL are not the same as those.

EVERY signal line of Verilog code inside the ALWAYS block are 'executed' at the same time. The same goes with the combinatorial logic outside of the ALWAYS block.

In your code, both the 

assign a=1'b1;

assign a=1'b0;

Will happen at the same time, no matter what.

The only way to change that is to put the last line inside your always block,after the end statement of the for loop.

One page that will give you some help on understanding the difference between C and Verilog is the page:EE-Times: The C Programmers Guide to Verilog

Upvotes: 4

user405725
user405725

Reputation:

Neither assign 1'b1; nor assign 1'b0; are valid assignments. If you want to constantly drive some net with 1'b1, then you have to write something like assign myvar = 1'b1;.

Also, if your intent was to actually assign to a, then always block doesn't make sense since a is the only thing in its sensitivity list meaning that that block must be executed whenever a changes its value. Since a will essentially never change its value, that block should never be executed.

It is hard to help you out unless you provide a minimal working example demonstrating your problem. The only thing that I can recommend is to use ternary operator in assign right hand side statement. That way you can model a behavioural logic without using always block. For example:

assign a = (b == 1'b1 ? c : 1'b0);

Hope it helps.

UPDATE:

Your second code example is neither complete nor legal as well. You cannot have two combinatorial assignments for the same net.

However, a sensitivity list in always block is now a star, which is Verilog 2001 notation to include all right hand side operands into a sensitivity list automatically. In your case, the block will get executed every time significand or lzero changes.

Upvotes: 2

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