CODEWITHSUNDEEP
verilog
Ofek Ron
Ofek Ron

Reputation: 8580

Combining Blocking and NonBlocking in Verilog

If I want statements to happen in parallel and another statement to happen when all other statements are done with, for example:

task read;
 begin
    if (de_if==NOP) begin 
        dp_op    <= 3'b000;
        dp_phase =  EXEC;
    end
    else begin
        if (de_if==EXEC_THEN) begin
            dp_const <= de_src3[0];
            dp_src   <= de_src3;
            dp_op    <= {NOP,de_ctrl3};
            dp_dest  <= de_dest1;
        end
        else if (get_value(de_ctrl1,de_src1)==dp_mem[de_src2]) begin
            dp_const <= de_src3[0];
            dp_src   <= de_src3;
            dp_op    <= {NOP,de_ctrl3};
            dp_dest  <= de_dest1;
        end 
        else begin
            dp_const <= de_src4[0];
            dp_src   <= de_src4;
            dp_op    <= {NOP,de_ctrl4};
            dp_dest  <= de_dest2;
        end
        #1 dp_phase=READ;
    end
 end
endtask

In this code I want the statement dp_phase = READ to only be executed after all other assignments are done, how do I do it?

As you can see what I did is wait 1 clock before the assignment but i do not know if this is how its done ...

Upvotes: 0

Views: 329

Answers (1)

user1619508
user1619508

Reputation:

You need a state machine. That's the canonical way to make things happen in a certain sequence. Try to remember that using a hardware description language is not like a regular programming language...you are just describing the kind of behavior that you would like the hardware to have.

To make a state machine you will need a state register, one or more flip-flops that keep track of where you are in the desired sequence of events. The flip-flops should be updated on the rising clock edge but the rest of your logic can be purely combinational.

Upvotes: 1

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