CODEWITHSUNDEEP
verilogblockingnonblocking
Mehdi
Mehdi

Reputation: 113

Verilog blocking and non-blocking in a sequence

I have the following in Verilog:

reg a;

always @ (clk)
begin
  a = 0;
  a <= 1;
  $display(a);
end

What value of literal 'a' would show me? Is that 0 or 1?

Upvotes: 2

Views: 1033

Answers (1)

chitranna
chitranna

Reputation: 1639

Verilog simulation occurs in 5 queues as stated in IEEE 1364-1995 § 5.3, IEEE 1364-2001 § 5.3, and IEEE 1364-2005 § 11.3:

  • Active Event (before #0)
    • Evaluate RHS of all non-blocking assignment
    • Evaluate RHS and change LHS of all blocking assignments
    • Evaluate RHS and change LHS of all continuous assignments
    • Evaluate inputs and change outputs of all primitives
    • Evaluate and print output from $display and $write
  • Inactive Event (after #0)
    • Evaluate RHS after #0 delay, otherwize same processes as Active Event
    • Callback procedures scheduled with PLI routines such as tf_synchronize()(deprecated in IEEE 1364-2005) and vpi_register_cb(cbReadWriteSynch)
  • NBA Update
    • Change LHS of all non-blocking assignments
  • Monitor Event
    • Evaluate and print output from $monitor and $strobe
    • Call PLI with reason_rosynchronize(deprecated in IEEE 1364-2005)
  • Future
    • Events to occur at some future simulation time

Since $display occurs before the non-blocking assignment is assigned , the value will be 0. Note the order of execution may change in each queue.

Upvotes: 3

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