CODEWITHSUNDEEP
verilognonblocking
hkn
hkn

Reputation: 123

verilog order of non-blocking statement

I have a question about the basics of non-blocking statement and for that I would like to start with a simple example.

Given: a=1, b=2, c=4, d=4, e=5

Example 1:

c <= a + b
d <= c + e

Example 2:

d <= c + e
c <= a + b

For both examples, the result would be the same c=3 and d = 9.

But what about this example:

a <= b
b <= a

Is it right, when I would say, that I have to look each row separately and the result would be a = 2 and b = 1 ?

And how about that:

a <= b
b <= c

Are the results: a = 2 and b = 4 or a = 4 and b = 4 ?

I would be happy, when I would get helpfully examples. Thank u forward :-)

Upvotes: 1

Views: 946

Answers (2)

Morgan
Morgan

Reputation: 20514

a = 1; 
b = 2;
c = 3; //assume this is meant to be 3?
d = 4;
e = 5;

c <= a + b ;// 1 + 2
d <= c + e ;// 3 + 5 (this is the old 3 not the new one)

Example 2: (from initial conditions)

d <= c + e; //3 + 5
c <= a + b; //1 + 2

But what about this example: (from initial conditions)

a <= b; // 2
b <= a; // 1

You are correct, assuming both lines executed in the same always process. 

a <= b; //2
b <= c; //3

user2484982 is correct think about it as creating temp variables that get assigned values at the start and the assignments to the real variable at the end of the process.

The rule of thumb is to use <= in always @(posedge clk) This models the behaviour of a flip-flop output.

Use = in an always @* for combinatorial logic, any change in input is instantly reflected.

Upvotes: 2

Reddy
Reddy

Reputation: 98

Hope u got ur answers from what morgan said.Non blocking assignments wiil be executed in two steps.First the RHS of all the expressions in that block will be calculated and then assigning them to LHS takes place. for example

a<=b; b<=c;

to be a little more explanatory it goes as follows

step1: temp_a=b and temp_b=c;
step2: a=temp_a and b=temp_b;

temp_a and temp_b are not actually created just for explanation

So for example

a<=b;b<=a

values of a and b get interchanged.

There is a good paper by Cumming's on blocking and non blocking assignments http://www.ece.cmu.edu/~ece447/s13/lib/exe/fetch.php?media=synth-verilog-cummins.pdf. This may be of some help.

Upvotes: 1

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