Reputation: 89
In Verilog,
#1 x = y;
#1; x = y;
are the same?
Also,
#1 x <= y;
#1; x <= y;
are the same?
I found a related link How does #delay work for verilog non blocking statements? and my question would solve the confusion more clearly.
Upvotes: 0
Views: 1384
Reputation: 13967
#1 x = y;
means wait one tick then assign y to x.
#1; x = y;
means wait one tick then do nothing then assign y to x. Both statements behave identically.
#1 x <= y;
means wait one tick then sample y in the active region then assign x in the NBA region.
#1; x <= y;
means wait one tick then do nothing then sample y in the active region then assign x in the NBA region. Again both statements behave identically.
However...
x = #1 y;
means sample y then wait one then assign to x in the active region one tick later; do not execute the following line until the delay is over.
x <= #1 y;
whilst means sample y then execute the following line immediately but schedule the assignment to x for the NBA region one tick in the future. The statements behave differently, neatly illustrating the reason why <=
is called the non-blocking assignment.
Placing a delay after the assignment operator like this is called an intra assignment delay.
Upvotes: 4
Reputation: 12354
delay here works in the following way. Assume the following:
initial begin
#1 do-something;
#1 do-something;
end
do-something
statement gets executedIt does not matter what type of the statement you have from the point of view of the delay model. In both your cases the execution of the block will span 2 ticks all together.
However, the statements themselves matter. Blocking assignment =
is not the same as non-blocking <=
. They behave differently and used for specific separate purposes. Though there are situations where the results of them might be identical.
In general, blocking assignments are always executed immediately in the block, whether non-blocking are guaranteed to be executed after all blocking assignments within a single simulation tick.
Upvotes: 0