How can I transform yosys gate primitives (e.g. $reduce_or) to simple gates and then pattern match those to more complex Verilog cells?

Question

I am new to Yosys, and I want to optimize arbitrary netlists to a set of complex cells.

For example's sake, let's consider an or-reductions:

red_or3x1_test.v

module test (A, Y);
    input [6:0] A;
    output Y;
    assign Y = |A;
endmodule

Source: https://yosyshq.readthedocs.io/projects/yosys/en/v0.48/yosys_internals/techmap.html

I want to use my own OR3 cell for this:

my_cells.v

module my_or3 (A, B, C, Y);

    input A, B, C;
    output Y;

    assign Y = A | B | C;

endmodule

For test cases where there are only $or yosys primitive cells I have succesfully used the extract command to do some substituions. However, for the or-reduction, Yosys generates a $or_reduce cell.

I have found that I can use the techmap command to transform the $or_reduce cell into a multitude of $_OR_ (i.e. not $or) cells, but now the extract command has no effect.

How do I best achieve this?

Reproducer:

reprod.ys

# Read modules from Verilog file
read_verilog red_or3x1_test.v

# Elaborate design hierarchy
hierarchy -check -top test

# Export first netlist diagram 
# Note: Expect to see `$reduce_or` cell
show -format svg -prefix reprod_show_1 test

#Convert $reduce_or (i.e. yosys gate primitive) to gates
techmap

# Export second netlist diagram 
# Note: Expect to see `$_OR_` gates, but ideally would want to just still get yosys gate primitives, i.e. `$or` 
show -format svg -prefix reprod_show_2 test

#Try to inject multi-inout cells
extract -map my_cells.v

# Export third netlist diagram
# Note: "extract" doesn't seem to work on "$_OR_" gates, tried other versions with only "$or" and was able to substitute in "my_or3"
show -format svg -prefix reprod_show_3 test