CODEWITHSUNDEEP
verilog
TRoa
TRoa

Reputation: 354

Using inputs as parameters in Verilog

Want to use inputs to be passed in range of another vector to extract corresponding value

Say for example see the Verilog code below.

But the problem is: I cant pass a variable(input) into the range of another variable. But this has to be done like that. Is there any other was to execute code with similar functionality? Actually my question pertains to the syntax correction of this code, and options available to execute similar functionality.

module foo(input1, input2, output1)
input [3:0] input1;
input [3:0] input2;
output reg [3:0] output1;
always@(*) begin
output1 <= input2[3:3-input1[1:0]];
end
endmodule

Upvotes: 0

Views: 1123

Answers (1)

Oldfart
Oldfart

Reputation: 6269

If you want to take a slice out of the vector you have to work around the unequal size on the RHS and LHS. This is such a solution:

always @( * )  
case (input1)
2'b00 : output1 = input2[3];
2'b01 : output1 = input2[3:2];
2'b10 : output1 = input2[3:1]; 
2'b11 : output1 = input2[3:0]; 
endcase

I find that somewhat sloppy. The following is the same but the vectors are equal size on the RHS and LHS:

always @( * )  
case (input1)
2'b00 : output1 = {3'b000,input2[3]  };
2'b01 : output1 = { 2'b00,input2[3:2]};
2'b10 : output1 = {  1'b0,input2[3:1]};
2'b11 : output1 =         input2[3:0];
endcase

You suddenly mention an 8-bit input. I assume you mean that input2 is 8 bits wide. But that requires only a maximum length of input1 of 3 bits. So the solution above would be a twice as big but still feasible.

Just for your sake here is a version for a 8 bit index which requires 256 bit vectors. :-) It is a bit more difficult to understand but also works for your specific case where you always need only the MS X bits. 

module foo( 
   input  [  7:0] input1,
   input  [255:0] input2,
   output [255:0] output1
);
wire [7:0] shift_right = 255-input;

   assign output1 = input2 >> shift_right ;

endmodule

Upvotes: 2

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