CODEWITHSUNDEEP
verilogsystem-veriloghdlsynthesisregister-transfer-level
Veridian
Veridian

Reputation: 3667

How to pass parameters to a verilog module when performing synthesis?

I have a parameterized verilog module with a bitwidth that is variable depending on the value given in `define WIDTH.

However, I would like to be able to somehow change the value of WIDTH by passing in a parameter during synthesis using design compiler.

I was wondering if there is a way to do this?

For instance, I'd like to be able to write the following for my input file for design compiler:

analyze -format sverilog -define WIDTH 10 myverilogfile.v

Upvotes: 1

Views: 3905

Answers (2)

Morgan
Morgan

Reputation: 20514

For Design Compiler the format is:

analyze -format sverilog -define WIDTH=10,DEPTH=128 myverilogfile.v

Upvotes: 4

BobH
BobH

Reputation: 86

Yes, most compilers will let you do this. It is tool-specific, though, there is no standard spec for this. The most common format to do this would be +define+WIDTH=10; you would have to check the documentation or help for your compiler though (or experiment)

Upvotes: 0

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