CODEWITHSUNDEEP
verilogsystem-verilogxilinxhdlsynthesis
mts
mts

Reputation: 3

passing 'generate' statement while instantiating a module in verilog

I have got a piece of verilog code, which i am trying to synthesize. There is a line in there, 

MUX2B_XB gas34 ( notPropSig, OECin, generate, notCoutSig );

instantiating a module. Where, the module implements a simple Boolean logic. But, synthesizer was giving an error:

Syntax error near "generate".

I can not understand the use of 'generate' statement in this context here while instantiation and also how to go about resolving the error without affecting the intended functionality.

Upvotes: 0

Views: 279

Answers (1)

Unn
Unn

Reputation: 5098

You seem to be trying to use generate as a variable name and connect that variable to the 3rd port of your module. However, generate is a Verilog keyword and cannot be used as a variable name (another example would be trying to use always as a variable like logic [1:0] always;, you cannot use such keywords as variable names). You simply need to change the name of that variable:

logic gen; // Or whatever the type and width of this line should be
...
MUX2B_XB gas34(notPropSig, OECin, gen, notCoutSig);

If you actually what to use the generate construct for something, you'll need to provide more context so we can help.

Upvotes: 5

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