CODEWITHSUNDEEP
verilog
user3380728
user3380728

Reputation: 131

verilog : Instantiation of modules in generate block with variable inputs

I have just started with verilog and trying to implement a small block where I want to call a module inside the generate block but with variable parameters, like:

module abc(a,b,c,d)
input a,b;
output c,d;

generate
if(a=1) begin
xyz xyz1(a,b,c,d);
end 
if(a=0) begin
efj xyz1(a,b,c,d);
endgenerate

endmodule

The values of a and b are changing at every clock cycle. I know we can only use constant values in generate block but how can I handle this? Is there any way out?

Upvotes: 2

Views: 1952

Answers (1)

Ari
Ari

Reputation: 7556

Looks like you need both modules simultaneously, so instantiate them without generate, but connect their outputs to the output of abc based on a's value:

module abc(a,b,c,d);
  input a,b;
  output reg c,d;
  wire c1, d1, c2, d2;
  xyz xyz1(a,b,c1,d1);
  efj xyz2(a,b,c2,d2);

  always @(*)
   if (a==1) begin 
     c=c1; d=d1;
   end
   else begin
     c=c2; d=d2;
   end

endmodule

Also, you should use == operator, rather than = operator in the if statements.

Upvotes: 1

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