CODEWITHSUNDEEP
indexingverilog
triplebig
triplebig

Reputation: 432

Instantiating multiple modules in Verilog

I am writing an 8-bit register comprised of D ffs, and I was wondering if I there is an easier way I could instantiate it in a more simple and easier way, other than what I have below.

module multiplicand(
    input [7:0] A,
    output [7:0] RA,
    input reset,
    input LOAD_cmd,
     input clk
    );

d_flipflop ff0(.D(A[0]), .Q(RA[0]) , .reset(reset), .clk(clk) );
d_flipflop ff1(.D(A[1]), .Q(RA[1]) , .reset(reset), .clk(clk) );
d_flipflop ff2(.D(A[2]), .Q(RA[2]) , .reset(reset), .clk(clk) );
d_flipflop ff3(.D(A[3]), .Q(RA[3]) , .reset(reset), .clk(clk) );
d_flipflop ff4(.D(A[4]), .Q(RA[4]) , .reset(reset), .clk(clk) );
d_flipflop ff5(.D(A[5]), .Q(RA[5]) , .reset(reset), .clk(clk) );
d_flipflop ff6(.D(A[6]), .Q(RA[6]) , .reset(reset), .clk(clk) );
d_flipflop ff7(.D(A[7]), .Q(RA[7]) , .reset(reset), .clk(clk) );

endmodule

Ideally I want to create a vector ff[7:0] that contains all the instantiations above.

Upvotes: 5

Views: 15280

Answers (1)

Morgan
Morgan

Reputation: 20554

From Verilog-95 you can have a vector of instances:

d_flipflop ff[7:0] (A, Q, reset clk);

Were A and Q are vectors width matched to the number of instances. My understanding is that since reset and clk are 1 bit the tools know to connect all instances to those 1 bit signals.

Upvotes: 10

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