CODEWITHSUNDEEP
vhdlverilog
pi3.14
pi3.14

Reputation: 5

Data conversion from VHDL to Verilog

I have the following variables defined in VHDL and I need to convert them into Verilog. I am first listing down the variables in VHDL and then my attempt at converting them:

VHDL Code

constant ValueLoad : std_logic_vector (11*24-1 downto 0) := 
b"0011010_0_0001111_000000000"&
b"0011010_0_0000000_000011111"&
b"0011010_0_0000001_000110111"&
b"0011010_0_0000010_001111001"&
b"0011010_0_0000011_000110000"&
b"0011010_0_0000100_011010010"&
b"0011010_0_0000101_000000001"&
b"0011010_0_0000110_001100010"&
b"0011010_0_0000111_001000011"&
b"0011010_0_0001000_000100000"&
b"0011010_0_0001001_000000001";


signal valueOut : std_logic;

signal registerA : std_logic_vector (11*24-1 downto 0); 
signal divider  : integer;
signal counterA : integer;
signal counterB : integer;

My attempt to convert to Verilog

wire valueOut;
wire [11*24-1:0] registerA;
wire divider;
wire counterA;
wire counterB;

Is this correct? Also, how do I define valueLoad in Verilog?

Upvotes: 0

Views: 572

Answers (2)

Greg
Greg

Reputation: 19122

It depends how they will be assigned. If there are assigned inside always blocks, then it should be reg or integer types.

reg valueOut;
reg [11*24-1:0] registerA;
integer divider;
integer counterA;
integer counterB;

If they are assigned via assign statements, then they need to be net types.

wire valueOut;
wire [11*24-1:0] registerA;
wire signed [31:0] divider; // 'signed' to allow negative numbers
wire signed [31:0] counterA;
wire signed [31:0] counterB;

VHDL's constant should map to Verilog's parameter. VHDL uses & for contamination, Verilog contaminates surrounding a comma separates list with curly brackets:

parameter [11*24-1:0] ValueLoad = { 
  24'b0011010_0_0001111_000000000,
  24'b0011010_0_0000000_000011111,
  24'b0011010_0_0000001_000110111,
  24'b0011010_0_0000010_001111001,
  24'b0011010_0_0000011_000110000,
  24'b0011010_0_0000100_011010010,
  24'b0011010_0_0000101_000000001,
  24'b0011010_0_0000110_001100010,
  24'b0011010_0_0000111_001000011,
  24'b0011010_0_0001000_000100000,
  24'b0011010_0_0001001_000000001  };

Upvotes: 2

ajcrm125
ajcrm125

Reputation: 333

Yes that looks correct. Here's one way to define ValueLoad:

parameter [11*24-1:0] ValueLoad =
{24'b0011010_0_0001111_000000000,
 24'b0011010_0_0000000_000011111,
 24'b0011010_0_0000001_000110111,
 24'b0011010_0_0000010_001111001,
 24'b0011010_0_0000011_000110000,
 24'b0011010_0_0000100_011010010,
 24'b0011010_0_0000101_000000001,
 24'b0011010_0_0000110_001100010,
 24'b0011010_0_0000111_001000011,
 24'b0011010_0_0001000_000100000,
 24'b0011010_0_0001001_000000001};

Upvotes: 0

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