CODEWITHSUNDEEP
translationvhdlverilog
ViktorK
ViktorK

Reputation: 3

Translate VHDL to Verilog

I have a problem with translating VHDL to Verilog. It's part of my source code on VHDL. With I/O I somehow understood, but have some problems to translate this string 

ib1 <= std_logic_vector(to_unsigned(i,ib1'length));

to verilog?

COMPONENT GenerateModel
PORT(
     ib1 : IN  std_logic_vector(3 downto 0);
    );
END COMPONENT;
--Inputs
signal ib1 : std_logic_vector(3 downto 0) := (others => '0');
 BEGIN
uut: GenerateModel PORT MAP (
      ib1 => ib1,
    );
process
begin
    for i in 0 to 15 loop
        ib1 <= std_logic_vector(to_unsigned(i,ib1'length));
        wait for 10 ns;
    end loop;
end process;
end;

Upvotes: 0

Views: 565

Answers (1)

Unn
Unn

Reputation: 5098

To extend into Verilog from Paebbels' comment, the line you are looking at does an explicit conversion from the type of the loop variable i to the port variable ib1. In Verilog, that explicit conversion is not needed, you can just assign the port variable directly. So, for example (in Verilog IEEE 1364-1995 compatible):

integer i;

...

for (i = 0; i < 16; i = i + 1) begin
  ib1 = i; // <-- The line
  #10; // -- Assume 1 step is 1 ns, can specific timescale if needed
end

If you want, you can even loop through the variable directly if its of type reg (ie, not a net):

for (ib1 = 0; ib1 < 15; ib1 = ib1 + 1) begin
  #10;
end
#10;

[Note that as Greg mentioned, you need to be sure you dont create an infinite loop as if ib1 is 4-bits wide, it will always be less than 16, thus I fixed the example above to loop until ib1 is 15 (4'b1111)]

Upvotes: 1

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