CODEWITHSUNDEEP
verilogvhdl
user20137958
user20137958

Reputation:

Converting Predefined Macros (Verilog) to VHDL

I came across this and was hoping someone could help me with it.

From my readings, the "Hello World" will only be printed during the simulation process. I would like to convert this Verilog code to VHDL. More specifically, I would like to use this feature in VHDL where I only want the code to be executed in simulation. Readings: https://docs.xilinx.com/r/2021.2-English/ug900-vivado-logic-simulation/Predefined-Macros

`ifdef XILINX_SIMULATOR 
   print "Hello World!";
`endif

However, I understand that there is no macro in VHDL. Is there any other way I can code such that the code is only executed during simulation? I am currently using Vivado ML Edition 2021.1.

Upvotes: 1

Views: 384

Answers (1)

dave_59
dave_59

Reputation: 42788

VHDL-2019 added conditional analysis. It would translate to

`if XILINX_SIMULATOR /= ""
   print "Hello World!"; 
`end if

However most tools do not support VHDL-2019, and Vivado does not even have full support of VHDL-2008.

But you can use comment pragmas

-- pragma translate_off
   print "Hello World!";
-- pragma translate_on

Upvotes: 0

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