CODEWITHSUNDEEP
vhdl
codedude
codedude

Reputation: 6519

Type of "variable" incompatible with type of "variable"

I'm getting the following error: from my VHDL project:

ERROR:HDLParsers:800 - "C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd" Line 90. Type of in_tilt is incompatible with type of tilt.

ERROR:HDLParsers:800 - "C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd" Line 91. Type of in_pan is incompatible with type of pan.

ERROR:HDLParsers:800 - "C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd" Line 92. Type of pwm_tilt is incompatible with type of pwm_tilt.

ERROR:HDLParsers:800 - "C:/Users/Theo/Desktop/Dropbox/ECE 120/Robotic Arm/top.vhd" Line 93. Type of pwm_pan is incompatible with type of pwm_pan.

Here's the applicable code. I have a top level VHDL module with the following code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all; 

entity top is
port (
  clk_in : in std_logic;
  pause : in std_logic;
  reset : in std_logic;
  switch : in std_logic_vector(3 downto 0);-----------------------------------------
  deb_in : in std_logic; ---from another switch
  deb_out : out std_logic; ---to test the debouncer
  pwm_pan : out std_logic_vector(7 downto 0);
  pwm_tilt : out std_logic_vector(7 downto 0)
);
end top;

the component declaration for PWM:

COMPONENT PWM
PORT(
     clk_100 : in  std_logic;
     reset : IN  std_logic;
        in_tilt : in std_logic;
        in_pan : in std_logic;
     pwm_pan : OUT  std_logic;
        pwm_tilt : out std_logic
    );
END COMPONENT;

Also the appropriate signals:

signal tilt : std_logic_vector (7 downto 0);
signal pan : std_logic_vector (7 downto 0);

and then later on this code: (This is where my error is appearing.)

    u1: PWM PORT MAP (
     clk_100 => clk_100,
     reset => reset,
--Line 90    in_tilt => tilt,
--Line 91   in_pan => pan,          
--Line 92    pwm_tilt => pwm_tilt,
--Line 93    pwm_pan => pwm_pan
);

This is the code in the PWM VHDL module:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all; 

entity PWM is
Port ( clk_100 : in  STD_LOGIC;
       reset : in  STD_LOGIC;
          in_tilt : in std_logic_vector( 7 downto 0);
          in_pan : in std_logic_vector( 7 downto 0);
          pwm_tilt : out std_logic_vector (7 downto 0);
          pwm_pan : out std_logic_vector (7 downto 0)
          );
end PWM;

Any idea what's causing this error? I hope I've included all the relevant code. Thanks.

Upvotes: 0

Views: 2028

Answers (2)

Jotorious
Jotorious

Reputation: 185

tilt is type std_logic.

in_tilt is type std_logic_vector.

The same for pan and in_pan. The types std_logic and std_logic_vector are generally incompatible (except when you have a slv of width 1).

Upvotes: 0

baldyHDL
baldyHDL

Reputation: 1387

in component declaration you declare in_tilt, in_pan, pwm_tilt and pwm_pan as std_logic. the signals you attatch later (tilt, pan, pwm_tilt, pwm_pan) are all std_logic_vectors! therefore these types are really incompatible ;-)

to solve this, adjust your component declaration and use std_logic_vector in the declaration as well!

Upvotes: 2

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