CODEWITHSUNDEEP
vhdl
user2481101
user2481101

Reputation: 97

getting undefined symbol error, even thought the variable is defined syntactically

architecture beh of pwm is 
begin
type lutable is array (1 to 64) of integer range 0 to 4000;
-----------------------------------------------tables for FULL STEPPING.
constant full_pwm1_1: lutable := (  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  
                                            3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  
                                            3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  
                                            3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900);
variable ds1_1: integer range 0 to 4000;        --Duty Cycle Variables for PWM1_1
variable c_full,c_half,c_quat,c_eigh,c_sixt: integer range 1 to 64;

process(gclk)
begin
case selectline is 
when "001" =>                    --------------------FULL STEPPING
            if dir='1' then--------------------direction selection
                    ds1_1 := full_pwm1_1(c_full);

all the other variables that i have not mentioned are defined as integers, with appropriate ranges, and have been all defined syntactically.

but i am getting an "undefined symbol" error for all of them and also, the full_pwm1_1 constant too. if someone could please help me and also verify if the array declaration and instantiation is correct?

Upvotes: 0

Views: 3132

Answers (2)

Martin Thompson
Martin Thompson

Reputation: 16792

Your types and constants declarations have to come after the architecture and before the begin.

Also, you can't have variables in this section - they have to either be

  • ordinary variables, within a process
  • shared variables... which must be of a protected type, not of normal types

Upvotes: 1

baldyHDL
baldyHDL

Reputation: 1387

write type and constant declaration between the "architecture" line and the "begin" line, e.g.:

architecture beh of pwm is 
   type lutable is array (1 to 64) of integer range 0 to 4000;
   constant full_pwm1_1: lutable := (  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  
                                        3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  
                                        3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  
                                        3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900,  3900,0,0,3900);

   ...
begin

   ...

write variable declarations between "process" and "begin", e.g.

process(gclk)    
    variable ds1_1: integer range 0 to 4000;        --Duty Cycle Variables for PWM1_1
    variable c_full,c_half,c_quat,c_eigh,c_sixt: integer range 1 to 64;
begin
    ...

or declare ds1_1 etc. as signals, e.g.:

...
   signal ds1_1: integer range 0 to 4000;        --Duty Cycle Variables for PWM1_1
   signal c_full,c_half,c_quat,c_eigh,c_sixt: integer range 1 to 64;
...
begin
    ...
    process(gclk)
       ...

Upvotes: 1

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