CODEWITHSUNDEEP
vhdl
TotoG
TotoG

Reputation: 17

VHDL - Object "x" is used but not declared

Im new to VHDL and I'm doing some university exercises. It was all great until today when I got an error that I don't understand the reason of why it appears. Hope you could help me. (Software: Quartus Prime)

Code:

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity AddSub4 is
 port(a, b : in std_logic_vector(3 downto 0);
        sub  : in std_logic;
        s    : out std_logic_vector(3 downto 0);
        cout : out std_logic);
end AddSub4;

architecture Structural of AddSub4 is

  signal s_b : std_logic_vector (3 downto 0);

begin
    
sub_mux: s_b <= b when (sub='0') else
            not b;

final: entity work.Adder4(Structural)
         port map(cin  => sub,
                     a    => a,
                     b    => b,
                     cout => cout,
                     s    => s);
end Structural;

architecture Behave of AddSub4 is

    signal val1, val2, valFinal : unsigned(4 downto 0);
    
begin

    val1     <= '0' & unsigned(a);
    val2     <= '0' & unsigned(b);
    valFinal <= (val1 + val2) when (sub = '0') else (val1 - val2);
    s        <= std_logic_vector(valFinal(3 downto 0));
    cout     <= std_logic(valFinal(4));

end Behave;

The error in the terminal:

Error (10482): VHDL error at AddSub4.vhd(30): object "unsigned" is used but not declared

Upvotes: 0

Views: 1086

Answers (1)

Ali Redha
Ali Redha

Reputation: 335

you need to add a library you can either

use ieee.numeric_std.all ; 
use ieee.std_logic_unsigned.all;

Upvotes: 1

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