CODEWITHSUNDEEP
vhdl
user1432402
user1432402

Reputation: 91

VHDL error - type of identifier does not agree

I'm new to VHDL, and I'm getting this error when I try to compile my code:

Error (10476): VHDL error at adder42.vhd(23): type of identifier "Cout" does not agree with its usage as std_logic_vector type

I'm not really sure what to change here, we've been given pretty much all the code here anyway, so I'm not sure if I've made a mistake in following the instructions, or there's something wrong with the code we've been given.

Here's the source:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY work;
USE work.fulladd_package.all;

ENTITY adder42 IS
    PORT( SW    : IN    STD_LOGIC_VECTOR(8 DOWNTO 0);
          LEDG  : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
          LEDR  : OUT   STD_LOGIC_VECTOR(1 DOWNTO 0));
END adder42;

ARCHITECTURE Structure OF adder42 IS
    SIGNAL c    : STD_LOGIC_VECTOR(1 TO 3);
    SIGNAL x, y : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL s    : STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL Cin, Cout: STD_LOGIC;
BEGIN
    Cin <= SW(8);
    x <= SW(3 DOWNTO 0);
    y <= SW(7 DOWNTO 4);
    LEDG <= s;
    LEDR <= Cout;

    stage0: fulladd PORT MAP( Cin, x(0), y(0), s(0), c(1));
    stage1: fulladd PORT MAP( c(1), x(1), y(1), s(1), c(2));
    stage2: fulladd PORT MAP( c(2), x(2), y(2), s(2), c(3));
    stage3: fulladd PORT MAP( c(3), x(3), y(3), s(3), Cout);
END Structure;

Upvotes: 1

Views: 8340

Answers (1)

Bill Lynch
Bill Lynch

Reputation: 81916

As Stark says in the comments, you're assigning a STD_LOGIC to a STD_LOGIC_VECTOR.

You could do:

LEDR <= Cout & Cout

But it all depends on what you want.

Upvotes: 1

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